diff options
| author | Alexis Savery <asavery@chromium.org> | 2023-08-30 20:11:34 +0000 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-09-06 13:17:34 +0000 |
| commit | 8ba64cd608e4e88e8ca34e04132cc0f39a1af5a2 (patch) | |
| tree | 86da42ace1fbfc54f702a63591bb8f34bd2dd42b /src/mainboard/google/puff/variants/faffy | |
| parent | 0d3745b67c9e457ad1401f3f1c322c1161231df3 (diff) | |
google/puff: Enable ASPM of RTL8111H
With kernel 5.15, puff hangs during power idle tests because
the NIC does not enter ASPM L1.2. We add "enable_aspm_l1_2" in
devicetree for RTL8111H to enable ASPM L1.2.
BUG=b:268859220, b:279618219
TEST=emerge and run power.Idle
Change-Id: I129dfd79e8112191453be513b2e3a260429b3030
Signed-off-by: Alexis Savery <asavery@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77570
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/puff/variants/faffy')
| -rw-r--r-- | src/mainboard/google/puff/variants/faffy/overridetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/puff/variants/faffy/overridetree.cb b/src/mainboard/google/puff/variants/faffy/overridetree.cb index f4b1a8b951..1a6838420a 100644 --- a/src/mainboard/google/puff/variants/faffy/overridetree.cb +++ b/src/mainboard/google/puff/variants/faffy/overridetree.cb @@ -428,6 +428,7 @@ chip soc/intel/cannonlake register "customized_leds" = "0x05af" register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" + register "enable_aspm_l1_2" = "1" device pci 00.0 on end end register "PcieRpSlotImplemented[6]" = "1" |