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authorMatt DeVillier <matt.devillier@gmail.com>2024-01-21 18:57:54 -0600
committerFelix Singer <service+coreboot-gerrit@felixsinger.de>2024-02-08 23:16:03 +0000
commit14a9f3e1d6e8e3848a8b0c57d90c06f5141dd2d8 (patch)
tree27b819e7ee6630a148fa8790d75b2e3c11b648ba /src/mainboard/google/puff/variants/baseboard
parent37601980fbef2caf0dd735fcf955b3169bc8a21f (diff)
mb/google/puff: Delegate I2C device configuration to overridetree
Don't enable the i2c controllers, since the variants will enable the ones they need individually in their overrridetrees. Disable gspi1 since all variants disable it in their overridetrees. TEST=tested with rest of patch train Change-Id: Ia9c67a8e05923a080e31d04721ecae4c810e82e8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Diffstat (limited to 'src/mainboard/google/puff/variants/baseboard')
-rw-r--r--src/mainboard/google/puff/variants/baseboard/devicetree.cb6
1 files changed, 0 insertions, 6 deletions
diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb
index 16f94daadd..6768711a3e 100644
--- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb
@@ -284,13 +284,8 @@ chip soc/intel/cannonlake
end
end
device ref sdxc on end
- device ref i2c0 on end
- device ref i2c1 on end
- device ref i2c2 on end
- device ref i2c3 on end
device ref heci1 on end
device ref sata on end
- device ref i2c4 on end
device ref pcie_rp9 on
# X4 NVME
register "PcieRpSlotImplemented[8]" = "1"
@@ -312,7 +307,6 @@ chip soc/intel/cannonlake
device spi 0 on end
end
end
- device ref gspi1 on end
device ref lpc_espi on
chip ec/google/chromeec
device pnp 0c09.0 on end