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authorFelix Singer <felixsinger@posteo.net>2020-07-29 22:28:37 +0200
committerMichael Niewöhner <c0d3z3r0@review.coreboot.org>2020-08-08 12:01:18 +0000
commit4d5c4e069cb99e715d04bf238e406a008f16707d (patch)
tree5614365c7b55999717ea40ff9c0de809830915d0 /src/mainboard/google/poppy/variants/soraka
parent88264ef30bcb20e8dd56de22cf564ebadd0bc2e9 (diff)
soc/intel/skylake: Enable SA IMGU depending on devicetree configuration
Currently, SA IMGU gets enabled by the option SaImguEnable, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the SA IMGU controller. All corresponding mainboards were checked if the devicetree configuration matches the SaImguEnable setting, and missing entries were added. Change-Id: I293a20a321c75f82a57cbd5339656d93509b7aa6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
Diffstat (limited to 'src/mainboard/google/poppy/variants/soraka')
-rw-r--r--src/mainboard/google/poppy/variants/soraka/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index af501561af..64ef501536 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -39,7 +39,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
- register "SaImguEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@@ -268,6 +267,7 @@ chip soc/intel/skylake
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on end # SA thermal subsystem
+ device pci 05.0 on end # SA IMGU
device pci 14.0 on end # USB xHCI
device pci 14.1 on end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem