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authorAngel Pons <th3fanbus@gmail.com>2021-02-20 00:16:47 +0100
committerAngel Pons <th3fanbus@gmail.com>2021-03-01 19:37:36 +0000
commit6bd99f9ada29f199f9bf50f1cd6b37e24ee1eb7b (patch)
tree951dd60f3e563bfbbc3c33c2f9c0fd4e1331e981 /src/mainboard/google/poppy/variants/rammus
parentba4cfb504ca1e8246d1ea135dfb566c3db5835cb (diff)
soc/intel/skylake: Clean up SD GPIO handling
This is to align with newer platforms. Change-Id: If33ea3a7835ec071be3fd060f9712c47678bd6bf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50963 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/poppy/variants/rammus')
-rw-r--r--src/mainboard/google/poppy/variants/rammus/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index 162b437f32..05f62e7767 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -232,7 +232,7 @@ chip soc/intel/skylake
register "tcc_offset" = "10" # TCC of 90C
# Use default SD card detect GPIO configuration
- register "sdcard_cd_gpio_default" = "GPP_E15"
+ register "sdcard_cd_gpio" = "GPP_E15"
device cpu_cluster 0 on
device lapic 0 on end