diff options
| author | Shaunak Saha <shaunak.saha@intel.com> | 2018-08-28 15:46:01 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-09-10 15:02:17 +0000 |
| commit | 261d626669ea244a55ec310a11a23ca56b609b51 (patch) | |
| tree | 25fb92501a3d23d211e7da34c6a2d2e5fc30374c /src/mainboard/google/poppy/variants/nocturne/devicetree.cb | |
| parent | ef250c47e4726c2648c96d1d06f7da45b221c359 (diff) | |
mb/google/poppy: Set UPD CmdTriStateDis for Nocturne
This patch sets the MRC UPD CmdTriStateDis for the
nocturne boards.Nocturne is LPDDR3 design without RTT
for CMD/CTRL.
BUG=b:111812662
TEST=Run memtester app and also webgl fishtank on
the LPDDR3 kabylake boards and also check the
margin data is proper in FSP.
Change-Id: I0f593761dcbd121e7e758421af178931b9d78295
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/28379
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/poppy/variants/nocturne/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/poppy/variants/nocturne/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index a6988fa4ec..3359a77d51 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -29,6 +29,9 @@ chip soc/intel/skylake # Enable S0ix register "s0ix_enable" = "1" + # Disable Command TriState + register "CmdTriStateDis" = "1" + # FSP Configuration register "ProbelessTrace" = "0" register "EnableLan" = "0" |