diff options
author | Furquan Shaikh <furquan@chromium.org> | 2018-01-24 13:14:33 -0800 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2018-01-26 17:25:15 +0000 |
commit | 8a1f095e50e068e42d378f47c79467e7b6295b7b (patch) | |
tree | ca7d7f2ca3daef0793a2303092404387635a28a7 /src/mainboard/google/poppy/variants/nautilus/gpio.c | |
parent | 9e17e11d8dcd706d7fb8d43e5cf1645efcfc2985 (diff) |
mb/google/poppy/variants/nautilus: Update camera power enable GPIOs
This change updates the camera power enable GPIOs as per the latest
schematics. With this update, since one of the enable GPIOs is using a
UART0 pin, set UART0 to PchSerialIoSkipInit in devicetree so that
FSP-S does not re-configure the UART0 GPIOs.
BUG=b:68964831
Change-Id: I5d9126ed8ca2b714f6276f4d3a24c243d7654774
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/poppy/variants/nautilus/gpio.c')
-rw-r--r-- | src/mainboard/google/poppy/variants/nautilus/gpio.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c index 2a76fd1e01..fea9da3542 100644 --- a/src/mainboard/google/poppy/variants/nautilus/gpio.c +++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c @@ -127,13 +127,13 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* C7 : SM1DATA ==> NC */ PAD_CFG_NC(GPP_C7), - /* C8 : UART0_RXD ==> NC */ - PAD_CFG_NC(GPP_C8), + /* C8 : UART0_RXD ==> CHP3_P3.3V_DX_WFCAM_EN */ + PAD_CFG_GPO(GPP_C8, 0, DEEP), /* C9 : UART0_TXD ==> CHP3_P3.3V_DX_DIG_EN */ PAD_CFG_GPO(GPP_C9, 0, DEEP), /* C10 : UART0_RTS# ==> CHP3_CAM_PMIC_RST_L */ PAD_CFG_GPO(GPP_C10, 1, DEEP), - /* C11 : UART0_CTS# ==> CHP3_P3.3V_DX_CAM_EN */ + /* C11 : UART0_CTS# ==> CHP3_P3.3V_DX_UFCAM_EN */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), |