diff options
| author | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-01-11 17:41:37 -0600 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-01-15 02:01:48 +0000 |
| commit | 4902e9b35f1b62c2c28e582e33ad55d2543f1483 (patch) | |
| tree | ecf83ae2983dbf3318bbb2bf315eee6cc3ed903d /src/mainboard/google/poppy/variants/nami/devicetree.cb | |
| parent | 2e6c55946c4d4ff04e1bc8de7272a4cef63ed55d (diff) | |
drivers/i2c/generic: Drop 'disable_gpio_export_in_crs' flag
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the
OS driver and ACPI thinking they own the GPIO. This can cause timing
problems because it's not clear which system should be controlling the
GPIO.
Previously, we flagged as an error any device which set the
'has_power_resource' flag but did not set 'disable_gpio_export_in_crs.'
There's no reason to require explicit disablement however, so drop the
superfluous 'disable' flag, and change the _CRS generation to check if
the GPIOs will be exported via the 'has_power_resource' flag instead.
BUG=b:265055477
TEST=build/boot skyrim, dump SSDT and verify touchscreen GPIOs only
listed under PRx, not under _CRS.
Change-Id: I837ae6c6fe4b8e1c4e10686406cba06bdb7759d2
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/mainboard/google/poppy/variants/nami/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/poppy/variants/nami/devicetree.cb | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 575c7a1ed0..2b1a19021c 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -318,7 +318,6 @@ chip soc/intel/skylake register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" register "generic.enable_delay_ms" = "45" register "generic.has_power_resource" = "1" - register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 20 on end end @@ -332,7 +331,6 @@ chip soc/intel/skylake register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" - register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 40 on end end @@ -366,7 +364,6 @@ chip soc/intel/skylake register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D3)" register "generic.reset_delay_ms" = "20" register "generic.has_power_resource" = "1" - register "generic.disable_gpio_export_in_crs" = "1" register "generic.wake" = "GPE0_DW2_01" register "hid_desc_reg_offset" = "0x1" device i2c 0x9 on end |