diff options
| author | Seunghwan Kim <sh_.kim@samsung.com> | 2018-09-03 20:25:50 +0900 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2018-09-06 05:07:08 +0000 |
| commit | c76e53ce30a13f77c0f3282a649ca4bfd84dede8 (patch) | |
| tree | 0659656a43f7c7461bedc1b80189566ed6da78ea /src/mainboard/google/poppy/romstage.c | |
| parent | 6d569e0c6b9a3e16d2a2c7276b26aba163b97dbc (diff) | |
mb/google/poppy/variants/nautilus: Bump VCC_SA voltage offset 75mV
Nautilus-Wifi with m3 AP got a halt issue during CTS test.
Nautilus-Wifi was FCS with Celeron AP first and also its PCB/BOM was
validated only with Celeron. Since Celeron deos not support turbo
boost mode, its steady power demend and lower CPU frequency may not
reflect the potential noise hidden inside the board.
Bumping VCC_SA voltage offset 75mV confirmed works to mitigate the
potential noise coupling to VCC_GT/SA, and we verified this change
makes this issue go away on Nautilus-Wifi board.
Nautilus-LTE doesn't show this issue, since it has 10L PCB, will have
better grounding and less noise/ripple than 8L PCB.
BUG=b:111417632
BRANCH=poppy
TEST=Verified CTS test pass without an issue.
Change-Id: Id13fcc36a5b6ed42620c66f57a7303f30bff1a50
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/28439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/poppy/romstage.c')
| -rw-r--r-- | src/mainboard/google/poppy/romstage.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/poppy/romstage.c b/src/mainboard/google/poppy/romstage.c index af4f70b4a3..bac1e17889 100644 --- a/src/mainboard/google/poppy/romstage.c +++ b/src/mainboard/google/poppy/romstage.c @@ -173,4 +173,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(p.type, p.use_sec_spd); mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; mem_cfg->MemorySpdDataLen = spd_info[p.type].len; + + mem_cfg->SaOcSupport = p.enable_sa_oc_support; + mem_cfg->SaVoltageOffset = p.sa_voltage_offset_val; } |