diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2016-12-14 12:10:21 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-12-19 17:51:24 +0100 |
| commit | 06cd903566b57af4698089de4a67dd49bf7e56ed (patch) | |
| tree | 4963d8de771a73d8fb46bc9d3f125b22bef319c1 /src/mainboard/google/poppy/dsdt.asl | |
| parent | 2911b5e509c273add2aee005d4bebff95e0e1116 (diff) | |
google/poppy: Add new board
Add poppy board files using kabylake and FSP 2.0.
BUG=chrome-os-partner:60713
BRANCH=None
TEST=Compiles successfully
Change-Id: Ic9aa5093b319690ae893a21cab98d9b843000e6c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17866
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard/google/poppy/dsdt.asl')
| -rw-r--r-- | src/mainboard/google/poppy/dsdt.asl | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl new file mode 100644 index 0000000000..c678dfcf24 --- /dev/null +++ b/src/mainboard/google/poppy/dsdt.asl @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "ec.h" +#include "gpio.h" + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + /* Some generic macros */ + #include <soc/intel/skylake/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/skylake/acpi/globalnvs.asl> + + /* CPU */ + #include <soc/intel/skylake/acpi/cpu.asl> + + Scope (\_SB) + { + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + } + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + /* Chrome OS specific */ + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chipset specific sleep states */ + #include <soc/intel/skylake/acpi/sleepstates.asl> + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } +} |