diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2017-03-20 10:53:57 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-03-21 22:35:06 +0100 |
| commit | 8110223989b34675c949465663c7ebfd5eb10155 (patch) | |
| tree | 9a114187a73feec17c1552d39823ce6870ad5abc /src/mainboard/google/poppy/devicetree.cb | |
| parent | bb5e77c4787c7bbf079d084087143c5ca85fdcc3 (diff) | |
mainboard/google/poppy: Use sideband IRQ for SD Card Detect
Since SD card controller is expected to enter D3hot by runtime power
management if there is no card inserted, we need to use a sideband IRQ
pin which is not under the control of the controller. Thus, configure
GPP_A7 as the sideband IRQ pin and pass it to OS as the card detect
pin.
BUG=b:35586693
BRANCH=None
TEST=Verified on a reworked poppy board that card detect works fine.
Change-Id: I4512f5d7829583e27c9750463396eaffbc5702b4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18926
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/google/poppy/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/poppy/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index fc639677fc..7bf28d0b31 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -177,7 +177,7 @@ chip soc/intel/skylake register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration - register "sdcard_cd_gpio_default" = "GPP_G7" + register "sdcard_cd_gpio_default" = "GPP_A7" device cpu_cluster 0 on device lapic 0 on end |