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| author | Maulik V Vaghela <maulik.v.vaghela@intel.corp-partner.google.com> | 2019-02-27 12:06:26 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-28 13:46:47 +0000 |
| commit | 64b82be3e3a7c6682b9b22b2ec5b5396f3e21512 (patch) | |
| tree | 034654c56a505e666d596efcd09d3c8cb7968eff /src/mainboard/google/peach_pit/memory.c | |
| parent | 67a489fdb058acfeda6e453ef145d8ac4cdc5971 (diff) | |
mb/google/hatch: Add GPIO programming for GPP_C0 to GPP_C7
coreboot did not program all GPIOs from C0 to C7 correctly which are
SMBUS GPIO. Some of the GPIOs are left in default mode which is
native function but we need to configure as GPIO mode and provide proper
configuration as per schematic.
After fixing GPIO, CSME power gating issue also gets fixed since SMBUS was not
getting idle due to GPIO configuration and CSME was not getting power
gated due to SMBUS.
BUG=b:123702553
BRANCH=none
TEST=Check on hatch board. CSME was not getting power gated for s0ix.
After applying this patch CSME is power gated now
Change-Id: I5c6b9310dcc7bade0023abd5524781ce71df28be
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/peach_pit/memory.c')
0 files changed, 0 insertions, 0 deletions