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authorMatt DeVillier <matt.devillier@gmail.com>2015-04-30 01:19:16 -0500
committerPatrick Georgi <pgeorgi@google.com>2015-04-30 17:50:47 +0200
commit31769d99da7f97150ddc30174c7cc315ca6e7b1f (patch)
tree9ad50867ffea7f90491754e1638f3f6e4bc0241c /src/mainboard/google/panther
parent40e2004abf4f763f38bfb12069b683554644734a (diff)
cpu/intel/haswell: remove dependency on socket_rpga989
Remove dependency of Haswell on cpu/intel/socket_rpga989 code, which is a carry-over from Sandy Bridge/Ivy Bridge and older coreboot conventions where features were structured around socket types. Add CPU-specific options to Kconfig and required subdirs to Makefile.inc which are curently included with socket_rpga989. TEST=successfully built and booted on google/panther Change-Id: Ic788e2928df107d11ea2d2eca7613490aaed395c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: http://review.coreboot.org/10037 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/panther')
-rw-r--r--src/mainboard/google/panther/Kconfig2
-rw-r--r--src/mainboard/google/panther/devicetree.cb4
2 files changed, 2 insertions, 4 deletions
diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig
index 6fdb46c303..f1721665d9 100644
--- a/src/mainboard/google/panther/Kconfig
+++ b/src/mainboard/google/panther/Kconfig
@@ -2,7 +2,7 @@ if BOARD_GOOGLE_PANTHER
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
- select CPU_INTEL_SOCKET_RPGA989
+ select CPU_INTEL_HASWELL
select NORTHBRIDGE_INTEL_HASWELL
select SOUTHBRIDGE_INTEL_LYNXPOINT
select INTEL_LYNXPOINT_LP
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index d37b622268..2032fd426b 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -10,10 +10,8 @@ chip northbridge/intel/haswell
register "gpu_dp_b_hotplug" = "0x06"
device cpu_cluster 0 on
- chip cpu/intel/socket_rPGA989
- device lapic 0 on end
- end
chip cpu/intel/haswell
+ device lapic 0 on end
# Magic APIC ID to locate this chip
device lapic 0xACAC off end