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authorSumeet Pawnikar <sumeet.r.pawnikar@intel.com>2018-03-23 23:30:43 +0530
committerAaron Durbin <adurbin@chromium.org>2018-04-04 16:19:56 +0000
commit65d2d21a0435fdc993ca6272cf40fabe6aa13b99 (patch)
treeeb114383926f9d41d2266eda109eecd7039dcf79 /src/mainboard/google/octopus
parent2f828ebb59fe680ccc6d75793d8c411996130883 (diff)
mb/google/octopus/variants/baseboard: Set PL1 and PL2 value
This patch sets PL1 value to ~6W. Here, 8W setting gives a run-time 6W actual measured power. Also, this patch sets PL2 value to 15W. BUG=None BRANCH=None TEST=Build and read the MSR 0x610. Change-Id: I2439a49b9917db0d9b05f333ce1c35003da493f6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/25341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/octopus')
-rw-r--r--src/mainboard/google/octopus/variants/baseboard/devicetree.cb7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
index 784dc9a158..aee8668a54 100644
--- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
@@ -33,6 +33,13 @@ chip soc/intel/apollolake
register "gpe0_dw2" = "PMC_GPE_N_95_64"
register "gpe0_dw3" = "PMC_GPE_NW_31_0"
+ # PL1 override 8000 mW: Due to error in the energy calculation for
+ # current VR solution. Experiments show that SoC TDP max (6W) can
+ # be reached when RAPL PL1 is set to 8W.
+ register "tdp_pl1_override_mw" = "8000"
+ # Set RAPL PL2 to 15W.
+ register "tdp_pl2_override_mw" = "15000"
+
# Minimum SLP S3 assertion width 28ms.
register "slp_s3_assertion_width_usecs" = "28000"