diff options
author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-05-09 15:37:09 +0530 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-26 15:09:09 +0000 |
commit | 2adb50d32e8cd9c61773b1d60de545255c6a4049 (patch) | |
tree | 0c78815666d0b53bf54130e9752690ba29e61c08 /src/mainboard/google/octopus | |
parent | a54bfd5e950ef108e9941a8319d0c24d786528ec (diff) |
apollolake: update processor power limits configuration
Update processor power limit configuration parameters based on
common code base support for Intel Apollo Lake SoC based platforms.
BRANCH=None
BUG=None
TEST=Built and tested on octopus system
Change-Id: I609744d165a53c8f91e42a67da1b972de00076a5
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41233
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/octopus')
-rw-r--r-- | src/mainboard/google/octopus/variants/baseboard/devicetree.cb | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 9253f11372..80e4873694 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -42,12 +42,14 @@ chip soc/intel/apollolake register "gpe0_dw2" = "PMC_GPE_N_95_64" register "gpe0_dw3" = "PMC_GPE_N_63_32" - # PL1 override 10000 mW: Due to error in the energy calculation for + # PL1 override 10 W: Due to error in the energy calculation for # current VR solution. Experiments show that SoC TDP max (6W) can # be reached when RAPL PL1 is set to 10W. - register "tdp_pl1_override_mw" = "10000" # Set RAPL PL2 to 15W. - register "tdp_pl2_override_mw" = "15000" + register "power_limits_config" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 15, + }" # Minimum SLP S3 assertion width 28ms. register "slp_s3_assertion_width_usecs" = "28000" |