diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2023-06-15 14:10:34 +0200 |
|---|---|---|
| committer | Jakub Czapiga <jacz@semihalf.com> | 2023-06-19 11:09:08 +0000 |
| commit | 1bbdd0ad012c97fa52d843be9f7b4db337649613 (patch) | |
| tree | bd1bdfc31dc50f05cfc198dfc607d3f8b2fcc009 /src/mainboard/google/octopus | |
| parent | 67fa48323551ea0e51b026740805a1d567b89897 (diff) | |
soc/intel/apollolake: Switch to snake case for PmicPmcIpcCtrl
For a unification of the naming convension, change from pascal case to
snake case style for parameter 'PmicPmcIpcCtrl'.
Change-Id: I3632d1e83108221d3487b4f175133ad347238bc5
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75853
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/octopus')
| -rw-r--r-- | src/mainboard/google/octopus/variants/baseboard/devicetree.cb | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index c001dbeb86..fdfcd61f51 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -275,18 +275,18 @@ chip soc/intel/apollolake # RegOrValue (15:8): 0x2 and RegAndValue (7:0) 0xF8. # The register is defined as: D[7:3] RSVD, D[2:0] PWROKDELAY. # uint8 RegOrValue, RegAndValue, PmicReadReg - # RegOrValue = (UINT8)((PmicPmcIpcCtrl >> 8) & 0xff); - # RegAndValue = (UINT8)(PmicPmcIpcCtrl & 0xff); + # RegOrValue = (UINT8)((pmic_pmc_ipc_ctrl >> 8) & 0xff); + # RegAndValue = (UINT8)(pmic_pmc_ipc_ctrl & 0xff); # PmicReadReg &= RegAndValue; # PmicReadReg |= RegOrValue; # PmicReadReg value will be programmed into PMIC D[2:0] PWROKDELAY field # and D[7:3] RSVD will not be impacted. - # Configure PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay + # Configure pmic_pmc_ipc_ctrl for PMC to program PMIC PCH_PWROK delay # from 100ms to 10ms. # PWROKDELAY[2:0]: 000=2.5ms, 001=5.0ms, 010=10ms, 011=15ms, 100=20ms, # 101=50ms, 110=75ms, 111=100ms (default) - register "PmicPmcIpcCtrl" = "0x5e4302f8" + register "pmic_pmc_ipc_ctrl" = "0x5e4302f8" # FSP UPD to modify the Integrated Filter (IF) value # Set it to default value: 0x12 |