soc/intel/alderlake: Enable FSP_USES_CB_DEBUG_EVENT_HANDLER Kconfig

This patch uses the FSP event handler feature and updates with coreboot
native debug implementation to unify the debug library between coreboot
and FSP.

BUG=b:225544587
TEST=Able to build and boot Brya with the same FSP debug log before and
with this code changes.

Before:

Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
The 0th FV start address is 0x000F961B000, size is 0x00150000, handle is 0xF961B000
Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6

With this code change:

[SPEW ]  Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
[SPEW ]  Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
[SPEW ]  Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
[SPEW ]  The 0th FV start address is 0x000F95C0000, size is 0x00160000, handle is 0xF95C0000
[SPEW ]  Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
[SPEW ]  Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
[SPEW ]  Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4a0530a282657e379a00c3e7d0ed8148dd5e9196
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

0 files changed, 0 insertions, 0 deletions