mb/google/octopus: Add new board

Add octopus board using GLK soc. Copied base code from mainboard/intel/glkrvp.
TODO: Fix as per octopus schematic.

Change-Id: Ic8c25b3fafbfef31b8b3b802acb3bc53ee7146b6
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/23685
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

13 files changed, 411 insertions, 0 deletions

diff --git a/src/mainboard/google/octopus/variants/baseboard/Makefile.inc b/src/mainboard/google/octopus/variants/baseboard/Makefile.inc
new file mode 100644
index 0000000000..d2d344c5e0
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/baseboard/Makefile.inc
@@ -0,0 +1,10 @@
+bootblock-y += gpio.c
+
+romstage-y += boardid.c
+romstage-y += memory.c
+
+ramstage-y += boardid.c
+ramstage-y += gpio.c
+ramstage-y += nhlt.c
+
+smm-y += gpio.c
diff --git a/src/mainboard/google/octopus/variants/baseboard/boardid.c b/src/mainboard/google/octopus/variants/baseboard/boardid.c
new file mode 100644
index 0000000000..67b753e663
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/baseboard/boardid.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <ec/google/chromeec/ec.h>
+
+uint8_t __attribute__((weak)) variant_board_id(void)
+{
+	return google_chromeec_get_board_version();
+}
diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
new file mode 100644
index 0000000000..64e07c303e
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
@@ -0,0 +1,5 @@
+chip soc/intel/apollolake
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+end
diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c
new file mode 100644
index 0000000000..3d0355fca8
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/*
+ * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'
+ * table found in EDS vol 1, but some pins aren't grouped functionally in
+ * the table so those were moved for more logical grouping.
+ */
+static const struct pad_config gpio_table[] = {
+};
+
+const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+/* GPIOs needed prior to ramstage. */
+static const struct pad_config early_gpio_table[] = {
+};
+
+const struct pad_config *__attribute__((weak))
+variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/* GPIO settings before entering sleep. */
+static const struct pad_config sleep_gpio_table[] = {
+};
+
+const struct pad_config *__attribute__((weak))
+variant_sleep_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(sleep_gpio_table);
+	return sleep_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+};
+
+const struct cros_gpio *__attribute__((weak)) variant_cros_gpios(size_t *num)
+{
+	*num = ARRAY_SIZE(cros_gpios);
+	return cros_gpios;
+}
diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl
new file mode 100644
index 0000000000..264ebb0403
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+})
+
+Name (DTRT, Package () {
+})
+
+Name (MPPC, Package ()
+{
+})
diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h
new file mode 100644
index 0000000000..dccb0ef1be
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef BASEBOARD_EC_H
+#define BASEBOARD_EC_H
+
+#include <ec/google/chromeec/ec_commands.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)              |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid or power button or key press */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+	(MAINBOARD_EC_S5_WAKE_EVENTS |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
+
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS	(MAINBOARD_EC_S3_WAKE_EVENTS)
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN      GPE_EC_WAKE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+#define SIO_EC_MEMMAP_ENABLE     /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE       /* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K       /* Enable PS/2 Keyboard */
+
+#endif
diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/gpio.h
new file mode 100644
index 0000000000..4cb57011c1
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/gpio.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef BASEBOARD_GPIO_H
+#define BASEBOARD_GPIO_H
+
+#include <soc/gpio.h>
+
+/*
+ * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
+ * which is North community
+ */
+#define EC_SCI_GPI	GPE0A_ESPI_SCI_STS
+
+/* EC SMI */
+#define EC_SMI_GPI	GPIO_41
+
+#define GPE_EC_WAKE	GPE0_DW1_06
+
+#define GPIO_EC_IN_RW	GPIO_189
+
+#define GPIO_PCH_WP	GPIO_190
+
+#endif /* BASEBOARD_GPIO_H */
diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 0000000000..c278cdee26
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef BASEBOARD_VARIANTS_H
+#define BASEBOARD_VARIANTS_H
+
+#include <soc/gpio.h>
+#include <soc/meminit.h>
+#include <stdint.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* Return the board id for the current variant board. */
+uint8_t variant_board_id(void);
+
+/* The next set of functions return the gpio table and fill in the number of
+ * entries for each table. */
+const struct pad_config *variant_gpio_table(size_t *num);
+const struct pad_config *variant_early_gpio_table(size_t *num);
+const struct pad_config *variant_sleep_gpio_table(size_t *num);
+
+/* Baseboard default swizzle. Can be reused if swizzle is same. */
+extern const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle;
+/* Return LPDDR4 configuration structure. */
+const struct lpddr4_cfg *variant_lpddr4_config(void);
+/* Return memory SKU for the board. */
+size_t variant_memory_sku(void);
+
+/* Return ChromeOS gpio table and fill in number of entries. */
+const struct cros_gpio *variant_cros_gpios(size_t *num);
+
+/* Seed the NHLT tables with the board specific information. */
+struct nhlt;
+void variant_nhlt_init(struct nhlt *nhlt);
+
+#endif /* BASEBOARD_VARIANTS_H */
diff --git a/src/mainboard/google/octopus/variants/baseboard/memory.c b/src/mainboard/google/octopus/variants/baseboard/memory.c
new file mode 100644
index 0000000000..b708b5ca76
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/baseboard/memory.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/meminit.h>
+#include <variant/gpio.h>
+
+static const struct lpddr4_cfg lp4cfg = {
+};
+
+const struct lpddr4_cfg *__attribute__((weak)) variant_lpddr4_config(void)
+{
+	return &lp4cfg;
+}
+
+size_t __attribute__((weak)) variant_memory_sku(void)
+{
+	return 0;
+}
diff --git a/src/mainboard/google/octopus/variants/baseboard/nhlt.c b/src/mainboard/google/octopus/variants/baseboard/nhlt.c
new file mode 100644
index 0000000000..7439b73fd1
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/baseboard/nhlt.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <nhlt.h>
+#include <soc/nhlt.h>
+
+void __attribute__((weak)) variant_nhlt_init(struct nhlt *nhlt)
+{
+	/* 2 Channel DMIC array. */
+	if (!nhlt_soc_add_dmic_array(nhlt, 2))
+		printk(BIOS_ERR, "Added 2CH DMIC array.\n");
+
+	/* Dialog for Headset codec.
+	 * Headset codec is bi-directional but uses the same configuration
+	 * settings for render and capture endpoints.
+	 */
+	if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1))
+		printk(BIOS_ERR, "Added Dialog_7219 codec.\n");
+
+	/* MAXIM Smart Amps for left and right speakers. */
+	if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP5))
+		printk(BIOS_ERR, "Added Maxim_98357 codec.\n");
+}
diff --git a/src/mainboard/google/octopus/variants/octopus/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/octopus/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000000..f3ff04b5e9
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/octopus/include/variant/acpi/dptf.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/dptf.asl>
diff --git a/src/mainboard/google/octopus/variants/octopus/include/variant/ec.h b/src/mainboard/google/octopus/variants/octopus/include/variant/ec.h
new file mode 100644
index 0000000000..586f1064f4
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/octopus/include/variant/ec.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/octopus/variants/octopus/include/variant/gpio.h b/src/mainboard/google/octopus/variants/octopus/include/variant/gpio.h
new file mode 100644
index 0000000000..6d1ce5a0e4
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/octopus/include/variant/gpio.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif /* MAINBOARD_GPIO_H */