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authorIan Feng <ian_feng@compal.corp-partner.google.com>2021-05-07 14:24:54 +0800
committerPatrick Georgi <pgeorgi@google.com>2021-05-12 08:00:30 +0000
commit23e15b1223b3a608f04851c62bd1a87e0cc9e68d (patch)
tree574816414f316a01bcc5d96a7ac93d7ac3ae70d0 /src/mainboard/google/octopus/variants/fleex
parent2be6da1d49ea7abc5102a6bcc2b7749192032fb9 (diff)
mb/google/octopus/var/fleex: Add cs42l42 HSBIAS setting
Disable HSBIAS sense setting. BUG=b:184103445 TEST=boot to check cs42l42 is functional. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I12c0e0a0f7490d35d36fe8ccbc940f29e1bb7976 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vitaly Rodionov <vitaly.rodionov@cirrus.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/octopus/variants/fleex')
-rw-r--r--src/mainboard/google/octopus/variants/fleex/overridetree.cb1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb
index f0343cd69b..5007719002 100644
--- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb
@@ -148,6 +148,7 @@ chip soc/intel/apollolake
register "bias_lvls[2]" = "4"
register "bias_lvls[3]" = "1"
register "hs_bias_ramp_rate" = "HSBIAS_RAMP_SLOW"
+ register "hs_bias_sense_disable" = "true"
device i2c 48 on end
end
end # - I2C 5