diff options
| author | Hung-Te Lin <hungte@chromium.org> | 2014-04-08 20:03:40 +0800 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-12-15 20:17:48 +0100 |
| commit | 1a8e0af78b1886acc96d1e80be5871d287d148c5 (patch) | |
| tree | 1019c994ddb15910833a59b5c11254105ce6e528 /src/mainboard/google/nyan_big | |
| parent | 0c9cc5ee3be406901a52a8151408bb13253bf39b (diff) | |
tegra124: Setup clock PLLD by approximating display panel pixel clock.
PLLD, the clock for display, was previously hard-coded to 306MHz. To support
more different panels, we should calcualte PLLD by panel pixel clock
configuration.
Note existing pixel clock configurations for nyan* boards won't work (they used
to rely on hard-coded approximated values) so the device trees are also
modified.
BRANCH=none
BUG=chrome-os-partner:25933
TEST=emerge-nyan_big coreboot chromeos-bootimage
See panel correctly initialized and got DEV screen.
Original-Change-Id: I8d592f0cc044e7c4e4803c45955642e791210ad3
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/193565
(cherry picked from commit 4f9b793633ebb2d104b0544e3b72fa0d105951c4)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ib2cabbad60af010e872505e888eab485ba8c2916
Reviewed-on: http://review.coreboot.org/7762
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/nyan_big')
| -rw-r--r-- | src/mainboard/google/nyan_big/devicetree.cb | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/src/mainboard/google/nyan_big/devicetree.cb b/src/mainboard/google/nyan_big/devicetree.cb index 600bdbef7b..885445022e 100644 --- a/src/mainboard/google/nyan_big/devicetree.cb +++ b/src/mainboard/google/nyan_big/devicetree.cb @@ -79,15 +79,7 @@ chip soc/nvidia/tegra124 register "vsync_width" = "12" register "vback_porch" = "12" - # we *know* the pixel clock for this system. - # 1592 x 800 x 60Hz = 76416000 - register "pixel_clock" = "76416000" - register "pll_div" = "2" - - # use plld_out0 (ie, plld/2) as clock source - # plld -> plld_out0 -> pclk - # plld = plld_out0 * 2 = (pclk * pll_div) * 2 - # = 305664000Hz + register "pixel_clock" = "76400000" # link configurations register "lane_count" = "1" |