diff options
| author | Jon Murphy <jpmurphy@google.com> | 2023-03-29 18:39:15 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-04-20 21:59:11 +0000 |
| commit | 65b54c4f9aa0aecf7a3f8c0ddb07929c9b2c6162 (patch) | |
| tree | 5a3a8ac830482446eba877d552bf64f3d27335fe /src/mainboard/google/myst/variants/baseboard | |
| parent | 4f02875e01dbfd6d818037b957663f0fd97be50e (diff) | |
mb/google/myst: Add eSPI configuration
Add eSPI configuration for myst. Ensure the additional windows are used
and remove unnecessary addresses from the range used on skyrim.
BUG=b:275953893
TEST=builds
Change-Id: I7b40adec78d4e0b596596fa6e2951c79bd3bd8c7
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74110
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/myst/variants/baseboard')
3 files changed, 64 insertions, 0 deletions
diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb index fbc9e93216..466b2dcc1b 100644 --- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb @@ -1,5 +1,43 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip soc/amd/phoenix + + # eSPI Configuration + # TODO(b/276913952) bump clock back up to 33MHz once things seem to be working well. + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x62, + .size = 1, + }, + .generic_io_range[1] = { + .base = 0x66, + .size = 1, + }, + .generic_io_range[2] = { + .base = 0x800, /* EC_HOST_CMD_REGION0 */ + .size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */ + }, + .generic_io_range[3] = { + .base = 0x900, /* EC_LPC_ADDR_MEMMAP */ + .size = 255, /* EC_MEMMAP_SIZE */ + }, + .generic_io_range[4] = { + .base = 0x200, /* EC_LPC_ADDR_HOST_DATA */ + .size = 8, /* 0x200 - 0x207 */ + }, + + .io_mode = ESPI_IO_MODE_QUAD, + .op_freq_mhz = ESPI_OP_FREQ_16_MHZ, + .crc_check_enable = 1, + .alert_pin = ESPI_ALERT_PIN_OPEN_DRAIN, + .periph_ch_en = 1, + .vw_ch_en = 1, + .oob_ch_en = 0, + .flash_ch_en = 0, + + .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1), + }" + register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | GPIO_I2C2_SCL | GPIO_I2C3_SCL" diff --git a/src/mainboard/google/myst/variants/baseboard/gpio.c b/src/mainboard/google/myst/variants/baseboard/gpio.c index 0add7a0b89..b2eccfff6e 100644 --- a/src/mainboard/google/myst/variants/baseboard/gpio.c +++ b/src/mainboard/google/myst/variants/baseboard/gpio.c @@ -173,6 +173,23 @@ static const struct soc_amd_gpio bootblock_gpio_table[] = { /* TODO(b/275965982): Fill bootblock gpio configuration */ }; +static const struct soc_amd_gpio espi_gpio_table[] = { + /* ESPI_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* ESPI_CLK */ + PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), + /* ESPI1_DATA0 */ + PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), + /* ESPI1_DATA1 */ + PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), + /* ESPI1_DATA2 */ + PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), + /* ESPI1_DATA3 */ + PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), +}; + void baseboard_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) { *size = ARRAY_SIZE(base_gpio_table); @@ -185,6 +202,12 @@ __weak void variant_bootblock_gpio_table(const struct soc_amd_gpio **gpio, size_ *gpio = bootblock_gpio_table; } +void variant_espi_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) +{ + *size = ARRAY_SIZE(espi_gpio_table); + *gpio = espi_gpio_table; +} + __weak void variant_override_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) { *size = 0; diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h index 3f6954803f..a39d2bf742 100644 --- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h @@ -12,6 +12,9 @@ void baseboard_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); /* This function provides GPIO init in bootblock. */ void variant_bootblock_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); +/* This function provides GPIO settings for eSPI bus. */ +void variant_espi_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); + /* * This function allows variant to override any GPIOs that are different than the base GPIO * configuration provided by baseboard_gpio_table(). |