diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2021-04-08 11:43:59 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-09 06:25:06 +0000 |
| commit | c7d18636c098a08070c7cab7e8389b6c452351e7 (patch) | |
| tree | 4d9d1a173dab5f468d83dd0c286e2211e0657bdb /src/mainboard/google/mancomb/variants | |
| parent | 8af6b57788a0066a8b0d6264ae234e4131eefbd7 (diff) | |
mb/google/mancomb: Enable AP <-> H1 communication
BUG=b:182211161
TEST=builds
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I29be8572bc7bb366347eabe553be49775dec46a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Diffstat (limited to 'src/mainboard/google/mancomb/variants')
| -rw-r--r-- | src/mainboard/google/mancomb/variants/baseboard/devicetree.cb | 8 | ||||
| -rw-r--r-- | src/mainboard/google/mancomb/variants/baseboard/gpio.c | 6 |
2 files changed, 14 insertions, 0 deletions
diff --git a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb index 533e2b4faa..0a604a37f5 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb @@ -121,5 +121,13 @@ chip soc/amd/cezanne device pnp 0c09.0 on end end end + device ref i2c_3 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "desc" = ""Cr50 TPM"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)" + device i2c 50 on end + end + end end # domain end # chip soc/amd/cezanne diff --git a/src/mainboard/google/mancomb/variants/baseboard/gpio.c b/src/mainboard/google/mancomb/variants/baseboard/gpio.c index bcca693c51..cd86f9c69c 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/gpio.c +++ b/src/mainboard/google/mancomb/variants/baseboard/gpio.c @@ -163,6 +163,12 @@ static const struct soc_amd_gpio base_gpio_table[] = { /* Early GPIO configuration */ static const struct soc_amd_gpio early_gpio_table[] = { + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), /* ESPI1_DATA0 */ PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE), /* ESPI1_DATA1 */ |