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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-12 22:58:19 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-21 15:50:16 +0000 |
| commit | 58a89537931cd243c6ddbb9ff435bc5862fc64b0 (patch) | |
| tree | 513a5a682063919f1f6c99d638ba75e6fbc86c3a /src/mainboard/google/link | |
| parent | 4dfb5f1055b03d27a509272e1a68de45c3fa2266 (diff) | |
Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"
In the end it does not look like RCBA register offsets are fully
compatible over southbridges.
This reverts commit d2d2aef6a3222af909183fb96dc7bc908fac3cd4.
Is squashed with revert of "sb/intel/common: Fix conflicting OIC
register definition" 8aaa00401b68e5c5b6c07b0984e3e7c3027e3c2f.
Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google/link')
| -rw-r--r-- | src/mainboard/google/link/romstage.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index cc2ef22ab6..d9f00f4bc3 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -30,7 +30,6 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/common/gpio.h> #include "ec/google/chromeec/ec.h" #include <arch/cpu.h> @@ -104,9 +103,9 @@ void mainboard_rcba_config(void) DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ - RCBA16(EOIC) = 0x0100; + RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(EOIC); + (void) RCBA16(OIC); } static uint8_t *locate_spd(void) |