Add support for Google's Chromebook Pixel

Ladies and gentlemen, I'm very happy to announce coreboot support for
the latest and greatest Google Chromebook: The Chromebook Pixel.

See the link below for more information on the Chromebook Pixel, and
its exciting specs:
http://www.google.com/intl/en/chrome/devices/chromebooks.html#pixel

The device is running coreboot and open source firmware on the EC
(see ChromeEC commit for more information on that exciting topic)

Change-Id: I03d00cf391bbb1a32f330793fe9058493e088571
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2482
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

9 files changed, 667 insertions, 0 deletions

diff --git a/src/mainboard/google/link/acpi/chromeos.asl b/src/mainboard/google/link/acpi/chromeos.asl
new file mode 100644
index 0000000000..2f167d9d57
--- /dev/null
+++ b/src/mainboard/google/link/acpi/chromeos.asl
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Name(OIPG, Package() {
+	Package() { 0x001, 0,  9, "PantherPoint" }, // recovery button
+	Package() { 0x003, 1, 57, "PantherPoint" }, // firmware write protect
+})
diff --git a/src/mainboard/google/link/acpi/ec.asl b/src/mainboard/google/link/acpi/ec.asl
new file mode 100644
index 0000000000..dc4f2b9c97
--- /dev/null
+++ b/src/mainboard/google/link/acpi/ec.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* mainboard configuration */
+#include "../ec.h"
+
+/* ACPI code for EC functions */
+#include "../../../../ec/google/chromeec/acpi/ec.asl"
diff --git a/src/mainboard/google/link/acpi/ivybridge_pci_irqs.asl b/src/mainboard/google/link/acpi/ivybridge_pci_irqs.asl
new file mode 100644
index 0000000000..dd32379fac
--- /dev/null
+++ b/src/mainboard/google/link/acpi/ivybridge_pci_irqs.asl
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for IvyBridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 22 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 19 },
+			Package() { 0x001cffff, 1, 0, 20 },
+			Package() { 0x001cffff, 2, 0, 17 },
+			Package() { 0x001cffff, 3, 0, 18 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 19 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 20 },
+			// LPC devices			0:1f.0
+			Package() { 0x001fffff, 0, 0, 21 },
+			Package() { 0x001fffff, 1, 0, 22 },
+			Package() { 0x001fffff, 2, 0, 23 },
+			Package() { 0x001fffff, 3, 0, 16 },
+		})
+	} Else {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+		})
+	}
+}
+
diff --git a/src/mainboard/google/link/acpi/mainboard.asl b/src/mainboard/google/link/acpi/mainboard.asl
new file mode 100644
index 0000000000..a2778a0e1a
--- /dev/null
+++ b/src/mainboard/google/link/acpi/mainboard.asl
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Scope (\_SB) {
+	Device (LID0)
+	{
+		Name(_HID, EisaId("PNP0C0D"))
+		Method(_LID, 0)
+		{
+			Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
+			Return (\LIDS)
+		}
+
+		// EC_LID_OUT is GPIO15
+		Name(_PRW, Package(){0x1f, 0x05})
+	}
+
+	Device (PWRB)
+	{
+		Name(_HID, EisaId("PNP0C0C"))
+	}
+
+	Device (TPAD)
+	{
+		Name (_ADR, 0x0)
+		Name (_UID, 1)
+
+		// Report as a Sleep Button device so Linux will
+		// automatically enable it as a wake source
+		Name(_HID, EisaId("PNP0C0E"))
+
+		// Trackpad Wake is GPIO12
+		Name(_PRW, Package(){0x1c, 0x03})
+
+		Name(_CRS, ResourceTemplate()
+		{
+			// PIRQE -> GSI20
+			Interrupt (ResourceConsumer, Edge, ActiveLow) {20}
+
+			// SMBUS Address 0x4b
+			VendorShort (ADDR) {0x4b}
+		})
+	}
+
+	Device (TSCR)
+	{
+		Name (_ADR, 0x0)
+		Name (_UID, 2)
+
+		// Report as a Sleep Button device so Linux will
+		// automatically enable it as a wake source
+		Name(_HID, EisaId("PNP0C0E"))
+
+		// Touchscreen Wake is GPIO14
+		Name(_PRW, Package(){0x1e, 0x03})
+
+		Name(_CRS, ResourceTemplate()
+		{
+			// PIRQG -> GSI22
+			Interrupt (ResourceConsumer, Edge, ActiveLow) {22}
+
+			// SMBUS Address 0x4a
+			VendorShort (ADDR) {0x4a}
+		})
+	}
+
+	// Keyboard Backlight interface via EC
+	Device (KBLT) {
+		Name (_HID, EisaId("GGL0002"))
+		Name (_UID, 1)
+		Name (_ADR, 0)
+
+		// Read current backlight value
+		Method (KBQC, 0)
+		{
+			Return (\_SB.PCI0.LPCB.EC0.KBLV)
+		}
+
+		// Write new backlight value
+		Method (KBCM, 1)
+		{
+			Store (Arg0, \_SB.PCI0.LPCB.EC0.KBLV)
+		}
+	}
+}
diff --git a/src/mainboard/google/link/acpi/platform.asl b/src/mainboard/google/link/acpi/platform.asl
new file mode 100644
index 0000000000..8dec08d955
--- /dev/null
+++ b/src/mainboard/google/link/acpi/platform.asl
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+	// Remember the OS' IRQ routing choice.
+	Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+	/* Disable WWAN */
+	Store (Zero, GP36)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	/* Update AC status */
+	Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0)
+	if (LNotEqual (Local0, \PWRS)) {
+		Store (Local0, \PWRS)
+		Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80)
+	}
+
+	/* Update LID status */
+	Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0)
+	if (LNotEqual (Local0, \LIDS)) {
+		Store (Local0, \LIDS)
+		Notify (\_SB.LID0, 0x80)
+	}
+
+	Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000000..ee4221a03e
--- /dev/null
+++ b/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 16 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 19 },
+			Package() { 0x001cffff, 1, 0, 20 },
+			Package() { 0x001cffff, 2, 0, 17 },
+			Package() { 0x001cffff, 3, 0, 18 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 19 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 21 },
+			// LPC devices			0:1f.0
+			Package() { 0x001fffff, 0, 0, 17 },
+			Package() { 0x001fffff, 1, 0, 23 },
+			Package() { 0x001fffff, 2, 0, 16 },
+			Package() { 0x001fffff, 3, 0, 18 },
+		})
+	} Else {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+		})
+	}
+}
+
diff --git a/src/mainboard/google/link/acpi/superio.asl b/src/mainboard/google/link/acpi/superio.asl
new file mode 100644
index 0000000000..b1ef4aea15
--- /dev/null
+++ b/src/mainboard/google/link/acpi/superio.asl
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* mainboard configuration */
+#include "../ec.h"
+
+#define SIO_EC_MEMMAP_ENABLE     // EC Memory Map Resources
+#define SIO_EC_HOST_ENABLE       // EC Host Interface Resources
+#define SIO_EC_ENABLE_PS2K       // Enable PS/2 Keyboard
+#define SIO_EC_ENABLE_COM1       // Enable Serial Port 1
+
+/* ACPI code for EC SuperIO functions */
+#include "../../../../ec/google/chromeec/acpi/superio.asl"
diff --git a/src/mainboard/google/link/acpi/thermal.asl b/src/mainboard/google/link/acpi/thermal.asl
new file mode 100644
index 0000000000..357c096a17
--- /dev/null
+++ b/src/mainboard/google/link/acpi/thermal.asl
@@ -0,0 +1,219 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+	ThermalZone (CRIT)
+	{
+		// Thermal zone polling frequency: 5 seconds
+		Name (_TZP, 50)
+
+		// Convert from Degrees C to 1/10 Kelvin for ACPI
+		Method (CTOK, 1) {
+			// 10th of Degrees C
+			Multiply (Arg0, 10, Local0)
+
+			// Convert to Kelvin
+			Add (Local0, 2732, Local0)
+
+			Return (Local0)
+		}
+
+		// Threshold for OS to shutdown
+		Method (_CRT, 0, Serialized)
+		{
+			Return (CTOK (\TCRT))
+		}
+
+		Method (_TMP, 0, Serialized)
+		{
+			// Get CPU Temperature from TIN9/PECI via EC
+			Store (\_SB.PCI0.LPCB.EC0.TIN9, Local0)
+
+			// Check for sensor not present
+			If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) {
+				Return (CTOK(0))
+			}
+
+			// Check for sensor not powered
+			If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) {
+				Return (CTOK(0))
+			}
+
+			// Check for sensor bad reading
+			If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) {
+				Return (CTOK(0))
+			}
+
+			// Adjust by offset to get Kelvin
+			Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0)
+
+			// Convert to 1/10 Kelvin
+			Multiply (Local0, 10, Local0)
+			Return (Local0)
+		}
+	}
+
+	ThermalZone (THRM)
+	{
+		Name (_TC1, 0x02)
+		Name (_TC2, 0x05)
+
+		// Thermal zone polling frequency: 10 seconds
+		Name (_TZP, 100)
+
+		// Thermal sampling period for passive cooling: 2 seconds
+		Name (_TSP, 20)
+
+		// Convert from Degrees C to 1/10 Kelvin for ACPI
+		Method (CTOK, 1) {
+			// 10th of Degrees C
+			Multiply (Arg0, 10, Local0)
+
+			// Convert to Kelvin
+			Add (Local0, 2732, Local0)
+
+			Return (Local0)
+		}
+
+		// Threshold for OS to shutdown
+		Method (_CRT, 0, Serialized)
+		{
+			Return (CTOK (\TCRT))
+		}
+
+		// Threshold for passive cooling
+		Method (_PSV, 0, Serialized)
+		{
+			Return (CTOK (\TPSV))
+		}
+
+		// Processors used for passive cooling
+		Method (_PSL, 0, Serialized)
+		{
+			Return (\PPKG ())
+		}
+
+		Method (_TMP, 0, Serialized)
+		{
+			// Get Temperature from TIN# set in NVS
+			Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0)
+
+			// Check for sensor not present
+			If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) {
+				Return (CTOK(0))
+			}
+
+			// Check for sensor not powered
+			If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) {
+				Return (CTOK(0))
+			}
+
+			// Check for sensor bad reading
+			If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) {
+				Return (CTOK(0))
+			}
+
+			// Adjust by offset to get Kelvin
+			Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0)
+
+			// Convert to 1/10 Kelvin
+			Multiply (Local0, 10, Local0)
+			Return (Local0)
+		}
+
+		/* CTDP Down */
+		Method (_AC0) {
+			If (LLessEqual (\FLVL, 0)) {
+				Return (CTOK (\F0OF))
+			} Else {
+				Return (CTOK (\F0ON))
+			}
+		}
+
+		/* CTDP Nominal */
+		Method (_AC1) {
+			If (LLessEqual (\FLVL, 1)) {
+				Return (CTOK (\F1OF))
+			} Else {
+				Return (CTOK (\F1ON))
+			}
+		}
+
+		Name (_AL0, Package () { TDP0 })
+		Name (_AL1, Package () { TDP1 })
+
+		PowerResource (TNP0, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 0)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				Store (0, \FLVL)
+				\_SB.PCI0.MCHC.STND ()
+				Notify (\_TZ.THRM, 0x81)
+			}
+			Method (_OFF) {
+				Store (1, \FLVL)
+				\_SB.PCI0.MCHC.STDN ()
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+
+		PowerResource (TNP1, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 1)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				Store (1, \FLVL)
+				Notify (\_TZ.THRM, 0x81)
+			}
+			Method (_OFF) {
+				Store (1, \FLVL)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+
+		Device (TDP0)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 0)
+			Name (_PR0, Package () { TNP0 })
+		}
+
+		Device (TDP1)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 1)
+			Name (_PR0, Package () { TNP1 })
+		}
+	}
+}
+
diff --git a/src/mainboard/google/link/acpi/video.asl b/src/mainboard/google/link/acpi/video.asl
new file mode 100644
index 0000000000..3ececa912b
--- /dev/null
+++ b/src/mainboard/google/link/acpi/video.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+	// TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+	// TODO (no displays defined yet)
+}
+