google/lars: Copy from intel/kunimitsu

Change-Id: I95129e6f519735e236c9c13b16e21df25b9ea607
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12200
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

5 files changed, 436 insertions, 0 deletions

diff --git a/src/mainboard/google/lars/acpi/chromeos.asl b/src/mainboard/google/lars/acpi/chromeos.asl
new file mode 100644
index 0000000000..d3ab569251
--- /dev/null
+++ b/src/mainboard/google/lars/acpi/chromeos.asl
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include "../gpio.h"
+
+Name (OIPG, Package () {
+	/* No physical recovery GPIO. */
+	Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" },
+	/* Firmware write protect GPIO. */
+	Package () { 0x0003, 1, GPIO_PCH_WP, "INT344B:00" },
+})
diff --git a/src/mainboard/google/lars/acpi/dptf.asl b/src/mainboard/google/lars/acpi/dptf.asl
new file mode 100644
index 0000000000..742ba7186f
--- /dev/null
+++ b/src/mainboard/google/lars/acpi/dptf.asl
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#define DPTF_CPU_PASSIVE        80
+#define DPTF_CPU_CRITICAL       90
+#define DPTF_CPU_ACTIVE_AC0     90
+#define DPTF_CPU_ACTIVE_AC1     80
+#define DPTF_CPU_ACTIVE_AC2     70
+#define DPTF_CPU_ACTIVE_AC3     60
+#define DPTF_CPU_ACTIVE_AC4     50
+
+#define DPTF_TSR0_SENSOR_ID	0
+#define DPTF_TSR0_SENSOR_NAME	"TMP432_Internal"
+#define DPTF_TSR0_PASSIVE	48
+#define DPTF_TSR0_CRITICAL	70
+
+#define DPTF_TSR1_SENSOR_ID	1
+#define DPTF_TSR1_SENSOR_NAME	"TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE	60
+#define DPTF_TSR1_CRITICAL	70
+
+#define DPTF_TSR2_SENSOR_ID	2
+#define DPTF_TSR2_SENSOR_NAME	"TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE	55
+#define DPTF_TSR2_CRITICAL	70
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+	Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 },	/* 0.0A */
+})
+
+Name (DTRT, Package () {
+	/* CPU Throttle Effect on CPU */
+	Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 0 */
+	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+	/* Charger Effect on Temp Sensor 1 */
+	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
+#endif
+
+	/* CPU Effect on Temp Sensor 1 */
+	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 2 */
+	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+	0x2,		/* Revision */
+	Package () {	/* Power Limit 1 */
+		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
+		1600,	/* PowerLimitMinimum */
+		6000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		200	/* StepSize */
+	},
+	Package () {	/* Power Limit 2 */
+		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
+		8000,	/* PowerLimitMinimum */
+		8000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		1000	/* StepSize */
+	}
+})
+
+/* Include DPTF */
+#include <soc/intel/skylake/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/google/lars/acpi/ec.asl b/src/mainboard/google/lars/acpi/ec.asl
new file mode 100644
index 0000000000..10ca834a2c
--- /dev/null
+++ b/src/mainboard/google/lars/acpi/ec.asl
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* mainboard configuration */
+#include "../ec.h"
+#include "../gpio.h"
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* ACPI code for EC functions */
+#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/google/lars/acpi/mainboard.asl b/src/mainboard/google/lars/acpi/mainboard.asl
new file mode 100644
index 0000000000..4f6251b9de
--- /dev/null
+++ b/src/mainboard/google/lars/acpi/mainboard.asl
@@ -0,0 +1,253 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include "../gpio.h"
+
+#define BOARD_TOUCHPAD_I2C_ADDR			0x15
+#define BOARD_TOUCHPAD_IRQ			TOUCHPAD_INT_L
+
+#define BOARD_TOUCHSCREEN_I2C_ADDR		0x10
+#define BOARD_TOUCHSCREEN_IRQ			TOUCHSCREEN_INT_L
+
+#define BOARD_HP_MIC_CODEC_I2C_ADDR		0x1a
+#define BOARD_HP_MIC_CODEC_IRQ			MIC_INT_L
+#define BOARD_LEFT_SPEAKER_AMP_I2C_ADDR		0x34
+#define BOARD_RIGHT_SPEAKER_AMP_I2C_ADDR	0x35
+
+Scope (\_SB)
+{
+	Device (LID0)
+	{
+		Name (_HID, EisaId ("PNP0C0D"))
+		Method (_LID, 0)
+		{
+			Return (\_SB.PCI0.LPCB.EC0.LIDS)
+		}
+
+		Name (_PRW, Package () { GPE_EC_WAKE, 5 })
+	}
+
+	Device (PWRB)
+	{
+		Name (_HID, EisaId ("PNP0C0C"))
+	}
+}
+
+/*
+ * LPC Trusted Platform Module
+ */
+Scope (\_SB.PCI0.LPCB)
+{
+	#include <drivers/pc80/tpm/acpi/tpm.asl>
+}
+
+/*
+ * WLAN connected to Root Port 1
+ */
+Scope (\_SB.PCI0.RP01)
+{
+	Device (WLAN)
+	{
+		Name (_ADR, 0x00000000)
+		Name (_DDN, "Wireless LAN")
+		Name (_PRW, Package () { GPE_WLAN_WAKE, 3 })
+	}
+}
+
+Scope (\_SB.PCI0.I2C0)
+{
+	/* Touchscreen */
+	Device (ELTS)
+	{
+		Name (_HID, "ELAN0001")
+		Name (_DDN, "Elan Touchscreen")
+		Name (_UID, 1)
+		Name (_S0W, 4)
+
+		Name (_CRS, ResourceTemplate ()
+		{
+			I2cSerialBus (
+				BOARD_TOUCHSCREEN_I2C_ADDR,
+				ControllerInitiated,
+				400000,
+				AddressingMode7Bit,
+				"\\_SB.PCI0.I2C0",
+			)
+			Interrupt (ResourceConsumer, Edge, ActiveLow)
+			{
+				BOARD_TOUCHSCREEN_IRQ
+			}
+		})
+
+		Method (_STA)
+		{
+			Return (0xF)
+		}
+	}
+}
+
+Scope (\_SB.PCI0.I2C1)
+{
+	/* Touchpad */
+	Device (ELTP)
+	{
+		Name (_HID, "ELAN0000")
+		Name (_DDN, "Elan Touchpad")
+		Name (_UID, 1)
+		Name (_S0W, 4)
+
+		Name (_CRS, ResourceTemplate ()
+		{
+			I2cSerialBus (
+				BOARD_TOUCHPAD_I2C_ADDR,
+				ControllerInitiated,
+				400000,
+				AddressingMode7Bit,
+				"\\_SB.PCI0.I2C1",
+			)
+			Interrupt (ResourceConsumer, Edge, ActiveLow)
+			{
+				BOARD_TOUCHPAD_IRQ
+			}
+		})
+
+		Method (_STA)
+		{
+			Return (0xF)
+		}
+	}
+}
+
+Scope (\_SB.PCI0.I2C4)
+{
+	/* Headphone Codec */
+	Device (HPMC)
+	{
+		Name (_HID, "10508825")
+		Name (_DDN, "NAU88L25 Codec")
+		Name (_UID, 1)
+		Name (_DSD, Package () {
+			ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+			Package () {
+			/* Enable jack detection via JKDET pin */
+			Package () { "nuvoton,jkdet-enable", 1 },
+			/*
+			 * JKDET pin is pulled up by R389 on board.
+			 * JKDET pin polarity = active low
+			 */
+			Package () { "nuvoton,jkdet-pull-enable", 1 },
+			Package () { "nuvoton,jkdet-pull-up", 1 },
+			Package () { "nuvoton,jkdet-polarity", 1 },
+			/* VDDA(1.8) * 1.53 = 2.754 */
+			Package () { "nuvoton,micbias-voltage", 6 },
+			/* VREF Impedance = 125 kOhm */
+			Package () { "nuvoton,vref-impedance", 2 },
+			/*
+			 * Setup 4 buttons impedance according to
+			 * Android specification
+			 */
+			Package () { "nuvoton,sar-threshold-num", 4 },
+			Package () { "nuvoton,sar-threshold",
+				Package() { 0x0a, 0x14, 0x26, 0x73 } },
+			/*
+			 * Coeff 0-15 used to adjust threshold level
+			 * 0 for low resist range
+			 */
+			Package () { "nuvoton,sar-hysteresis", 0 },
+			/* SAR tracking gain based on 2.754 micbias-voltage */
+			Package () { "nuvoton,sar-voltage", 6 },
+			/* 100ms short key press debounce */
+			Package () { "nuvoton,short-key-debounce", 3 },
+			/* 2^(7+2) = 512 ms insert/eject debounce */
+			Package () { "nuvoton,jack-insert-debounce", 7 },
+			/* debounce not needed for eject normally */
+			Package () { "nuvoton,jack-eject-debounce", 0 },
+			}
+		})
+
+		Name (_CRS, ResourceTemplate()
+		{
+			I2cSerialBus (
+				BOARD_HP_MIC_CODEC_I2C_ADDR,
+				ControllerInitiated,
+				400000,
+				AddressingMode7Bit,
+				"\\_SB.PCI0.I2C4",
+			)
+			Interrupt (ResourceConsumer, Level, ActiveLow)
+			{
+				BOARD_HP_MIC_CODEC_IRQ
+			}
+		})
+
+		Method (_STA)
+		{
+			Return (0xF)
+		}
+	}
+
+	/* Left Speaker Amp */
+	Device (SPKL)
+	{
+		Name (_HID, "INT343B")
+		Name (_DDN, "SSM4567 Speaker Amp")
+		Name (_UID, 0)
+
+		Name (_CRS, ResourceTemplate()
+		{
+			I2cSerialBus (
+				BOARD_LEFT_SPEAKER_AMP_I2C_ADDR,
+				ControllerInitiated,
+				400000,
+				AddressingMode7Bit,
+				"\\_SB.PCI0.I2C4",
+			)
+		})
+
+		Method (_STA)
+		{
+			Return (0xF)
+		}
+	}
+
+	/* Right Speaker Amp */
+	Device (SPKR)
+	{
+		Name (_HID, "INT343B")
+		Name (_DDN, "SSM4567 Speaker Amp")
+		Name (_UID, 1)
+
+		Name (_CRS, ResourceTemplate()
+		{
+			I2cSerialBus (
+				BOARD_RIGHT_SPEAKER_AMP_I2C_ADDR,
+				ControllerInitiated,
+				400000,
+				AddressingMode7Bit,
+				"\\_SB.PCI0.I2C4",
+			)
+		})
+
+		Method (_STA)
+		{
+			Return (0xF)
+		}
+	}
+}
diff --git a/src/mainboard/google/lars/acpi/superio.asl b/src/mainboard/google/lars/acpi/superio.asl
new file mode 100644
index 0000000000..822821e9df
--- /dev/null
+++ b/src/mainboard/google/lars/acpi/superio.asl
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* mainboard configuration */
+#include "../ec.h"
+
+#define SIO_EC_MEMMAP_ENABLE     // EC Memory Map Resources
+#define SIO_EC_HOST_ENABLE       // EC Host Interface Resources
+#define SIO_EC_ENABLE_PS2K       // Enable PS/2 Keyboard
+
+/* ACPI code for EC SuperIO functions */
+#include <ec/google/chromeec/acpi/superio.asl>