summaryrefslogtreecommitdiff
path: root/src/mainboard/google/lars/acpi
diff options
context:
space:
mode:
authorLin Huang <hl@rock-chips.com>2016-07-11 17:09:53 +0800
committerMartin Roth <martinroth@google.com>2016-07-28 23:54:39 +0200
commit3707fc2d961720152e7e96bc1606b893023cb577 (patch)
treea0223588b335927c25fb0ef709ae90e46fb598a3 /src/mainboard/google/lars/acpi
parentdf5ead9d2d01a03c4c3b00a1cb95c4e4b373bf1a (diff)
google/gru & kevin: Update DRAM configuration
We need to enable DRAM ODT on kevin/gru board to improve the DRAM signal. Note, if the DRAM ODT is enabled and set to 120ohms, the sdram VREF need to adjust to 840mv. This patch also makes following changes: 1. For compatiblity with the old board, add the "sdram-lpddr3-hynix-4GB-666-no-odt.inc" and "sdram-lpddr3-hynix-4GB-800-no-odt.inc" files which do not enable sdram ODT. 2. Delete the 300MHz dram inc file. The 300MHz sdram config just reduced 666MHz to 300MHz based on the 666MHz config file, and it is not stable, so delete it. 3. Delete the 928MHz dram inc file, 928MHz sdram config still in debuging, delete it for now. BRANCH=none BUG=chrome-os-partner:54871 TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass Change-Id: If0248e1bc4cef2c298762080f1ca018653af0521 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 78d8a28e2d3489c99c9bba2c1c9aa76812e2e33f Original-Change-Id: I35f0685782d6fb178a95780ec77c45f565dd2194 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/358763 Original-Commit-Ready: Dan Shi <dshi@chromium.org> Original-Tested-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15813 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/lars/acpi')
0 files changed, 0 insertions, 0 deletions