summaryrefslogtreecommitdiff
path: root/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD9GQFSM-046-4GB.c
diff options
context:
space:
mode:
authorJessy Jiang <jiangchao5@huaqin.corp-partner.google.com>2021-03-02 16:56:07 +0800
committerHung-Te Lin <hungte@chromium.org>2021-03-08 01:49:33 +0000
commit69da75411218c705b6b7375664523be707cb5258 (patch)
tree091acdf1790eaea1cfe019ba520e761d449b6640 /src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD9GQFSM-046-4GB.c
parent30c5e607b3cc49ce8a45e420ffa0e71691b86d7d (diff)
mb/google/kukui: Add Micron 4GB discrete LPDDR4X DDR support
Support 4G+128G MT29VZZZAD9GQFSM-046 W.9S9 discrete DDR bootup. BUG=b:162292216 BRANCH=kukui TEST=Boots correctly on Kukui. Signed-off-by: Jessy Jiang <jiangchao5@huaqin.corp-partner.google.com> Change-Id: I5657a007154bc52c6f0f27e1de6e3294a5e74ad7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD9GQFSM-046-4GB.c')
-rw-r--r--src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD9GQFSM-046-4GB.c27
1 files changed, 27 insertions, 0 deletions
diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD9GQFSM-046-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD9GQFSM-046-4GB.c
new file mode 100644
index 0000000000..0caa1302cb
--- /dev/null
+++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD9GQFSM-046-4GB.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/dramc_param.h>
+
+struct sdram_params params = {
+ .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG,
+ .ddr_geometry = DDR_TYPE_2CH_1RK_4GB_4,
+ .frequency = 1600,
+ .wr_level = {
+ [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} },
+ [CHANNEL_B] = { {0x21, 0x28}, {0x21, 0x29} }
+ },
+ .cbt_cs_dly = {
+ [CHANNEL_A] = {0x2, 0x2},
+ [CHANNEL_B] = {0x2, 0x2}
+ },
+ .cbt_final_vref = {
+ [CHANNEL_A] = {0x5E, 0x5E},
+ [CHANNEL_B] = {0x5E, 0x5C}
+ },
+ .emi_cona_val = 0xF053F154,
+ .emi_conh_val = 0x44440003,
+ .emi_conf_val = 0x00421000,
+ .chn_emi_cona_val = {0x0444F051, 0x0444F051},
+ .cbt_mode_extern = CBT_NORMAL_MODE,
+ .delay_cell_unit = 868,
+};