soc/amd: commonize generation of the PIC/APIC mapping tables

Now that we have a common init_tables in all mainboards using AMD SoCs,
both the population of the fch_pic_routing and fch_apic_routing arrays
and the definition of those arrays can be moved to the common AMD SoC
code to not have the code duplicated in all mainboards.

BUG=b:182782749

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I8c65eca258272f0ef7dec3ece6236f5d00954c66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68853
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 3 insertions, 38 deletions

diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c
index 3433f8bcaa..9cbfd4be46 100644
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -18,17 +18,8 @@
 #include <variant/ec.h>
 #include <variant/thermal.h>
 
-/*
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system.  It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair.  These values are chipset and mainboard
- * dependent and should be updated accordingly.
- */
-static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES];
-static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES];
-
+/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
+   accessed via I/O ports 0xc00/0xc01. */
 static const struct fch_irq_routing fch_irq_map[] = {
 	{ PIRQ_A,	 3,		16 },
 	{ PIRQ_B,	 4,		17 },
@@ -61,35 +52,12 @@ static const struct fch_irq_routing fch_irq_map[] = {
 	{ PIRQ_MISC2,	0x00,	0x00 },
 };
 
-static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
+const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
 {
 	*length = ARRAY_SIZE(fch_irq_map);
 	return fch_irq_map;
 }
 
-static void init_tables(void)
-{
-	const struct fch_irq_routing *mb_irq_map;
-	size_t mb_fch_irq_mapping_table_size;
-	size_t i;
-
-	mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size);
-
-	memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
-	memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
-
-	for (i = 0; i < mb_fch_irq_mapping_table_size; i++) {
-		if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) {
-			printk(BIOS_WARNING,
-			       "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n",
-			       mb_irq_map[i].intr_index, i);
-			continue;
-		}
-		fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num;
-		fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num;
-	}
-}
-
 /*
  * This table defines the index into the picr/intr_data tables for each
  * device.  Any enabled device and slot that uses hardware interrupts should
@@ -117,8 +85,6 @@ static void pirq_setup(void)
 {
 	pirq_data_ptr = mainboard_pirq_data;
 	pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
-	intr_data_ptr = fch_apic_routing;
-	picr_data_ptr = fch_pic_routing;
 }
 
 void __weak variant_devtree_update(void)
@@ -165,7 +131,6 @@ static void mainboard_init(void *chip_info)
  *************************************************/
 static void mainboard_enable(struct device *dev)
 {
-	init_tables();
 	/* Initialize the PIRQ data structures for consumption */
 	pirq_setup();