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authorMartin Roth <martinroth@google.com>2018-09-17 09:16:31 -0600
committerMartin Roth <martinroth@google.com>2018-09-18 21:15:45 +0000
commitc3f5293da7a1d4e14a9cf8b38567f9ca3c427a4e (patch)
treea42968688bcbef7f7bef3f40471bbe30263d24bc /src/mainboard/google/kahlee/variants/baseboard
parent6b3038efc0c49fb4b1b4de77151b756fee376e37 (diff)
mainboard/google/kahlee: Set EMMC reset pin to output low
While the pin was set to a pull-down, with the external pull-up, this wasn't enough to keep the pin low. Set to output low to drive to 0V. TEST=Boot grunt, verify EMMC_BRIDGE_RST is 0V. BUG=b:115661061 Change-Id: Ife014b8a879274df5d892c1de386976808de1df0 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/google/kahlee/variants/baseboard')
-rw-r--r--src/mainboard/google/kahlee/variants/baseboard/gpio.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
index 75a8ab5e3f..95064bccdf 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
@@ -54,7 +54,7 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
/* GPIO_40 - EMMC_BRIDGE_RST */
- PAD_GPI(GPIO_40, PULL_DOWN),
+ PAD_GPO(GPIO_40, LOW),
/* GPIO_70 - WLAN_PE_RST_L */
PAD_GPO(GPIO_70, HIGH),