diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-10-20 23:06:56 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-24 15:50:39 +0000 |
| commit | 34362d0c0f9a27c6eab62e59f83be11e4dfb617a (patch) | |
| tree | dd0279a89d94a26e4852474eb98962a2bfab0adb /src/mainboard/google/kahlee/variants/baseboard | |
| parent | fed17f968d7687f803c6654898ba99f8d4567d1d (diff) | |
mb/google/kahlee: use override devicetrees for variants
This helps with deduplicating the identical parts of the variants'
devicetrees.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie050c4624327b904e8cb0959b40421339e43f825
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/kahlee/variants/baseboard')
| -rw-r--r-- | src/mainboard/google/kahlee/variants/baseboard/devicetree.cb | 99 |
1 files changed, 99 insertions, 0 deletions
diff --git a/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb new file mode 100644 index 0000000000..e900acd4fe --- /dev/null +++ b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb @@ -0,0 +1,99 @@ + +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/amd/stoneyridge + register "spd_addr_lookup" = " + { + { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 + }" + register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" + register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" + register "uma_size" = "32 * MiB" + + register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ + GPIO_I2C2_SCL | GPIO_I2C3_SCL" + + device domain 0 on + device ref iommu off end # IOMMU (Disabled for performance and battery) + device ref gfx on end + device ref gfx_hda on end + device ref gpp_bridge_1 on end # WLAN + device ref gpp_bridge_3 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end + end + device ref hda_bridge on end + device ref hda on end + device ref xhci on end + device ref ehci on end + device ref lpc_bridge on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device ref sdhci on end + end #domain + + device ref i2c_0 on + chip drivers/generic/adau7002 + device generic 0.0 on end + end + chip drivers/i2c/da7219 + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_14)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + register "mclk_name" = ""oscout1"" + device i2c 1a on end + end + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_119)" + register "sdmode_delay" = "5" + device generic 0.1 on end + end + end + device ref i2c_1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "desc" = ""Cr50 TPM"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + device i2c 50 on end + end + end + device ref i2c_2 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" + register "wake" = "7" + device i2c 15 on end + end + end + device ref i2c_3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + end +end #chip soc/amd/stoneyridge |