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authorChris Ching <chingcodes@google.com>2018-02-06 10:28:49 -0700
committerAaron Durbin <adurbin@chromium.org>2018-02-21 23:36:22 +0000
commit97ab880082505b4aa0d4b2a058e850bd3376d9b8 (patch)
treed099da762a2be578eac58592fdbc1ee5e49e413d /src/mainboard/google/kahlee/variants/baseboard/include
parent2269a3c328c335aa57d7094ca24a9d21ee6ade7d (diff)
mainboard/google/kahlee: Add tis_plat_irq_status
For variants that have a cr50 tpm, this enables faster polling when interacting with the tpm. BUG=b:72838769 BRANCH=none TEST=verified on grunt that irq is used and not timeouts for tpm Change-Id: I5786d334b6c1cc70f4c7107c75b07a7e27ac4428 Signed-off-by: Chris Ching <chingcodes@chromium.org> Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/kahlee/variants/baseboard/include')
-rw-r--r--src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h
index e237ce24fe..1e349b7c2e 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h
@@ -24,6 +24,9 @@
# define MEM_CONFIG2 GPIO_131
# define MEM_CONFIG3 GPIO_132
+/* CR50 interrupt pin */
+#define H1_PCH_INT GPIO_9
+
/* SPI Write protect */
#define CROS_WP_GPIO GPIO_122
#define GPIO_EC_IN_RW GPIO_15