summaryrefslogtreecommitdiff
path: root/src/mainboard/google/hatch
diff options
context:
space:
mode:
authorNick Vaccaro <nvaccaro@google.com>2020-02-04 20:40:47 -0800
committerPatrick Georgi <pgeorgi@google.com>2020-02-11 07:52:47 +0000
commit75f0124c44a26aa2d71bb3cba7cdc42e224980ce (patch)
treefe7b07bb3fd2a8d42010de683ae180e5f3282acb /src/mainboard/google/hatch
parent5b43484db3b41ec2b9664ef73b7e613eed813374 (diff)
mb/google/volteer: use new Tiger Lake memory config
Some of the common memory code that was being performed in mainboard has moved into the soc to reduce redundant code. This change adapts volteer to use Tiger Lake's new common code. BUG=b:145642089, b:145238504, b:145564831 BRANCH=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer, boot to kernel, "cat /proc/meminfo" and verify it reports "MemTotal: 8038196 kB". Change-Id: I32c9b8a040728d44565806eece6cf60b6b6073b6 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/hatch')
0 files changed, 0 insertions, 0 deletions