summaryrefslogtreecommitdiff
path: root/src/mainboard/google/hatch
diff options
context:
space:
mode:
authorMartin Roth <martin@coreboot.org>2021-10-01 14:37:30 -0600
committerMartin Roth <martinroth@google.com>2021-10-05 18:06:52 +0000
commit50863daef8ed75c0cb3dfd375e7622c898de5821 (patch)
treecbb2dea518524f8c9ce5edca5d57132ca9705086 /src/mainboard/google/hatch
parent0949e739066c3509e05db2b9ed71cefaaa62205f (diff)
src/mainboard to src/security: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/google/hatch')
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index f78d42096d..a84eabde5c 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -44,7 +44,7 @@ chip soc/intel/cannonlake
register "tcc_offset" = "10" # TCC of 90C
# Unlock GPIO pads
register "PchUnlockGpioPads" = "1"
- # SD card WP pin confguration
+ # SD card WP pin configuration
register "ScsSdCardWpPinEnabled" = "0"
# NOTE: if any variant wants to override this value, use the same format