diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2022-09-07 17:21:01 -0500 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-09-22 15:35:19 +0000 |
| commit | 45b1da33c80a4b1328794a5a59c93d1988cee4f1 (patch) | |
| tree | 7f7c7c6b7c44632c72b2a5bc717f74bcf678f7c8 /src/mainboard/google/hatch | |
| parent | 826b45b69b9dd492771798679d3a8223a954217f (diff) | |
mb/google/hatch: split up hatch and puff baseboards
The hatch and puff baseboards have diverged enough to where it makes
more sense to split them into separate boards. Copy the mb/google/hatch
directory into a new dir 'puff' and strip out all boards and items
related to the hatch baseboard. Remove all puff-related items from the
original hatch directory. Clean up and alphabetize Kconfig selections.
Test: build and boot akemi hatch variant and wyvern puff variant.
Change-Id: I8c7350f3afcff3ddefc6fa14054a3f9257568cd3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62970
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/hatch')
73 files changed, 13 insertions, 7775 deletions
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 2d8ee15766..3522787c3c 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -1,4 +1,4 @@ -config BOARD_GOOGLE_HATCH_COMMON +config BOARD_GOOGLE_BASEBOARD_HATCH def_bool n select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_GPIO_KEYS @@ -17,6 +17,7 @@ config BOARD_GOOGLE_HATCH_COMMON select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select HAVE_SPD_IN_CBFS select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 @@ -24,57 +25,17 @@ config BOARD_GOOGLE_HATCH_COMMON select SOC_INTEL_COMETLAKE_1 select SOC_INTEL_COMMON_BLOCK_DTT select SPI_TPM - select TPM_GOOGLE_CR50 - -config BOARD_GOOGLE_BASEBOARD_HATCH - def_bool n - select BOARD_GOOGLE_HATCH_COMMON select SYSTEM_TYPE_LAPTOP - -config BOARD_GOOGLE_BASEBOARD_PUFF - def_bool n - select BOARD_GOOGLE_HATCH_COMMON - select DRIVERS_INTEL_DPTF - select ROMSTAGE_SPD_SMBUS - select RT8168_GEN_ACPI_POWER_RESOURCE - select RT8168_GET_MAC_FROM_VPD - select RT8168_SET_LED_MODE - select SOC_INTEL_CSE_LITE_SKU - select SPD_READ_BY_WORD - select FW_CONFIG - select FW_CONFIG_SOURCE_CHROMEEC_CBI + select TPM_GOOGLE_CR50 config BOARD_GOOGLE_AKEMI select BOARD_GOOGLE_BASEBOARD_HATCH select INTEL_GMA_HAVE_VBT -config BOARD_GOOGLE_AMBASSADOR - select BOARD_GOOGLE_BASEBOARD_PUFF - -config BOARD_GOOGLE_DOOLY - select BOARD_GOOGLE_BASEBOARD_PUFF - select INTEL_GMA_HAVE_VBT - config BOARD_GOOGLE_DRATINI select BOARD_GOOGLE_BASEBOARD_HATCH select INTEL_GMA_HAVE_VBT -config BOARD_GOOGLE_DUFFY_LEGACY - select BOARD_GOOGLE_BASEBOARD_PUFF - select BOARD_ROMSIZE_KB_32768 - select INTEL_GMA_HAVE_VBT - -config BOARD_GOOGLE_DUFFY - select BOARD_GOOGLE_BASEBOARD_PUFF - select INTEL_GMA_HAVE_VBT - -config BOARD_GOOGLE_FAFFY - select BOARD_GOOGLE_BASEBOARD_PUFF - select INTEL_GMA_HAVE_VBT - -config BOARD_GOOGLE_GENESIS - select BOARD_GOOGLE_BASEBOARD_PUFF - config BOARD_GOOGLE_HATCH select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_32768 @@ -97,15 +58,6 @@ config BOARD_GOOGLE_JINLON select DRIVERS_GFX_GENERIC select INTEL_GMA_HAVE_VBT -config BOARD_GOOGLE_KAISA_LEGACY - select BOARD_GOOGLE_BASEBOARD_PUFF - select BOARD_ROMSIZE_KB_32768 - select INTEL_GMA_HAVE_VBT - -config BOARD_GOOGLE_KAISA - select BOARD_GOOGLE_BASEBOARD_PUFF - select INTEL_GMA_HAVE_VBT - config BOARD_GOOGLE_KINDRED select BOARD_GOOGLE_BASEBOARD_HATCH select INTEL_GMA_HAVE_VBT @@ -115,9 +67,6 @@ config BOARD_GOOGLE_KOHAKU select BOARD_GOOGLE_BASEBOARD_HATCH select INTEL_GMA_HAVE_VBT -config BOARD_GOOGLE_MOONBUGGY - select BOARD_GOOGLE_BASEBOARD_PUFF - config BOARD_GOOGLE_MUSHU select BOARD_GOOGLE_BASEBOARD_HATCH select INTEL_GMA_HAVE_VBT @@ -128,42 +77,25 @@ config BOARD_GOOGLE_NIGHTFURY select DRIVERS_I2C_MAX98390 select INTEL_GMA_HAVE_VBT -config BOARD_GOOGLE_NOIBAT - select BOARD_GOOGLE_BASEBOARD_PUFF - select INTEL_GMA_HAVE_VBT - config BOARD_GOOGLE_PALKIA select BOARD_GOOGLE_BASEBOARD_HATCH select CHROMEOS_DSM_CALIB if CHROMEOS select DRIVERS_I2C_RT1011 -config BOARD_GOOGLE_PUFF - select BOARD_GOOGLE_BASEBOARD_PUFF - select BOARD_ROMSIZE_KB_32768 - select INTEL_GMA_HAVE_VBT - -config BOARD_GOOGLE_SCOUT - select BOARD_GOOGLE_BASEBOARD_PUFF - -config BOARD_GOOGLE_WYVERN - select BOARD_GOOGLE_BASEBOARD_PUFF - select INTEL_GMA_HAVE_VBT - -if BOARD_GOOGLE_HATCH_COMMON +if BOARD_GOOGLE_BASEBOARD_HATCH config DISABLE_HECI1_AT_PRE_BOOT - default y if BOARD_GOOGLE_BASEBOARD_HATCH + default y config CHROMEOS - select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if !ROMSTAGE_SPD_SMBUS + select CHROMEOS_DRAM_PART_NUMBER_IN_CBI select EC_GOOGLE_CHROMEEC_SWITCHES - select GBB_FLAG_FORCE_DEV_SWITCH_ON - select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_DEV_BOOT_ALTFW + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_MANUAL_RECOVERY select HAS_RECOVERY_MRC_CACHE select VBOOT_LID_SWITCH - select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if SOC_INTEL_CSE_LITE_SKU config CHROMEOS_WIFI_SAR bool "Enable SAR options for ChromeOS build" @@ -179,37 +111,15 @@ config DEVICETREE config DIMM_MAX default 2 -config ROMSTAGE_SPD_CBFS - bool - default y if !ROMSTAGE_SPD_SMBUS - select HAVE_SPD_IN_CBFS - -config ROMSTAGE_SPD_SMBUS - bool - default n - select SPD_CACHE_IN_FMAP - config DRIVER_TPM_SPI_BUS default 0x1 config UART_FOR_CONSOLE default 0 -if BOARD_GOOGLE_BASEBOARD_HATCH config FMDFILE - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-hatch-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 && CHROMEOS - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-hatch-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 && CHROMEOS -endif - -if BOARD_GOOGLE_BASEBOARD_PUFF -config FMDFILE - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-puff-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 && CHROMEOS - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-puff-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 && CHROMEOS - -config POWER_OFF_ON_CR50_UPDATE - bool - default n -endif + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 && CHROMEOS + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 && CHROMEOS config MAINBOARD_DIR default "google/hatch" @@ -221,28 +131,15 @@ config MAINBOARD_FAMILY config MAINBOARD_PART_NUMBER default "Akemi" if BOARD_GOOGLE_AKEMI default "Dratini" if BOARD_GOOGLE_DRATINI - default "Duffy" if BOARD_GOOGLE_DUFFY - default "Duffy" if BOARD_GOOGLE_DUFFY_LEGACY - default "Faffy" if BOARD_GOOGLE_FAFFY default "Hatch" if BOARD_GOOGLE_HATCH default "Helios" if BOARD_GOOGLE_HELIOS default "Helios_Diskswap" if BOARD_GOOGLE_HELIOS_DISKSWAP default "Jinlon" if BOARD_GOOGLE_JINLON - default "Kaisa" if BOARD_GOOGLE_KAISA - default "Kaisa" if BOARD_GOOGLE_KAISA_LEGACY default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU default "Mushu" if BOARD_GOOGLE_MUSHU - default "Noibat" if BOARD_GOOGLE_NOIBAT - default "Palkia" if BOARD_GOOGLE_PALKIA default "Nightfury" if BOARD_GOOGLE_NIGHTFURY - default "Puff" if BOARD_GOOGLE_PUFF - default "Wyvern" if BOARD_GOOGLE_WYVERN - default "Dooly" if BOARD_GOOGLE_DOOLY - default "Ambassador" if BOARD_GOOGLE_AMBASSADOR - default "Genesis" if BOARD_GOOGLE_GENESIS - default "Scout" if BOARD_GOOGLE_SCOUT - default "Moonbuggy" if BOARD_GOOGLE_MOONBUGGY + default "Palkia" if BOARD_GOOGLE_PALKIA config OVERRIDE_DEVICETREE default "variants/helios_diskswap/overridetree.cb" if BOARD_GOOGLE_HELIOS_DISKSWAP @@ -255,28 +152,15 @@ config TPM_TIS_ACPI_INTERRUPT config VARIANT_DIR default "akemi" if BOARD_GOOGLE_AKEMI default "dratini" if BOARD_GOOGLE_DRATINI - default "duffy" if BOARD_GOOGLE_DUFFY - default "duffy" if BOARD_GOOGLE_DUFFY_LEGACY - default "faffy" if BOARD_GOOGLE_FAFFY default "hatch" if BOARD_GOOGLE_HATCH default "helios" if BOARD_GOOGLE_HELIOS default "helios" if BOARD_GOOGLE_HELIOS_DISKSWAP default "jinlon" if BOARD_GOOGLE_JINLON - default "kaisa" if BOARD_GOOGLE_KAISA - default "kaisa" if BOARD_GOOGLE_KAISA_LEGACY default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU default "mushu" if BOARD_GOOGLE_MUSHU - default "noibat" if BOARD_GOOGLE_NOIBAT - default "palkia" if BOARD_GOOGLE_PALKIA default "nightfury" if BOARD_GOOGLE_NIGHTFURY - default "puff" if BOARD_GOOGLE_PUFF - default "wyvern" if BOARD_GOOGLE_WYVERN - default "dooly" if BOARD_GOOGLE_DOOLY - default "ambassador" if BOARD_GOOGLE_AMBASSADOR - default "genesis" if BOARD_GOOGLE_GENESIS - default "scout" if BOARD_GOOGLE_SCOUT - default "moonbuggy" if BOARD_GOOGLE_MOONBUGGY + default "palkia" if BOARD_GOOGLE_PALKIA config VBOOT select HAS_RECOVERY_MRC_CACHE @@ -285,8 +169,4 @@ config VBOOT config USE_PM_ACPI_TIMER default n -config EDK2_BOOT_TIMEOUT - int - default 5 if BOARD_GOOGLE_BASEBOARD_PUFF - -endif # BOARD_GOOGLE_HATCH_COMMON +endif # BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 1307314e9a..0564476468 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -3,27 +3,9 @@ comment "Hatch" config BOARD_GOOGLE_AKEMI bool "-> Akemi (IdeaPad Flex 5/5i Chromebook)" -config BOARD_GOOGLE_AMBASSADOR - bool "-> Ambassador" - -config BOARD_GOOGLE_DOOLY - bool "-> Dooly" - config BOARD_GOOGLE_DRATINI bool "-> Dratini (HP Pro c640 Chromebook)" -config BOARD_GOOGLE_DUFFY_LEGACY - bool "-> Duffy Legacy (32MB)" - -config BOARD_GOOGLE_DUFFY - bool "-> Duffy (ASUS Chromebox 4)" - -config BOARD_GOOGLE_FAFFY - bool "-> Faffy (ASUS Fanless Chromebox)" - -config BOARD_GOOGLE_GENESIS - bool "-> Genesis" - config BOARD_GOOGLE_HATCH bool "-> Hatch" @@ -36,38 +18,17 @@ config BOARD_GOOGLE_HELIOS_DISKSWAP config BOARD_GOOGLE_JINLON bool "-> Jinlon (HP Elite c1030 Chromebook)" -config BOARD_GOOGLE_KAISA_LEGACY - bool "-> Kaisa Legacy (32MB)" - -config BOARD_GOOGLE_KAISA - bool "-> Kaisa (Acer Chromebox CXI4)" - config BOARD_GOOGLE_KINDRED bool "-> Kindred (Acer Chromebook 712)" config BOARD_GOOGLE_KOHAKU bool "-> Kohaku (Samsung Galaxy Chromebook)" -config BOARD_GOOGLE_MOONBUGGY - bool "-> Moonbuggy" - config BOARD_GOOGLE_MUSHU bool "-> Mushu" config BOARD_GOOGLE_NIGHTFURY bool "-> Nightfury (Samsung Galaxy Chromebook 2)" -config BOARD_GOOGLE_NOIBAT - bool "-> Noibat (HP Chromebox G3)" - config BOARD_GOOGLE_PALKIA bool "-> Palkia" - -config BOARD_GOOGLE_PUFF - bool "-> Puff" - -config BOARD_GOOGLE_SCOUT - bool "-> Scout" - -config BOARD_GOOGLE_WYVERN - bool "-> Wyvern (CTL Chromebox CBx2)" diff --git a/src/mainboard/google/hatch/chromeos-hatch-16MiB.fmd b/src/mainboard/google/hatch/chromeos-16MiB.fmd index 8880a4f9fe..8880a4f9fe 100644 --- a/src/mainboard/google/hatch/chromeos-hatch-16MiB.fmd +++ b/src/mainboard/google/hatch/chromeos-16MiB.fmd diff --git a/src/mainboard/google/hatch/chromeos-hatch-32MiB.fmd b/src/mainboard/google/hatch/chromeos-32MiB.fmd index 8368b0a44b..8368b0a44b 100644 --- a/src/mainboard/google/hatch/chromeos-hatch-32MiB.fmd +++ b/src/mainboard/google/hatch/chromeos-32MiB.fmd diff --git a/src/mainboard/google/hatch/chromeos-puff-16MiB.fmd b/src/mainboard/google/hatch/chromeos-puff-16MiB.fmd deleted file mode 100644 index 61a0b0fbb4..0000000000 --- a/src/mainboard/google/hatch/chromeos-puff-16MiB.fmd +++ /dev/null @@ -1,44 +0,0 @@ -FLASH@0xff000000 0x1000000 { - SI_ALL@0x0 0x300000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x2ff000 - } - SI_BIOS@0x300000 0xd00000 { - RW_SECTION_A@0x0 0x3e8000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3d7fc0 - RW_FWID_A@0x3e7fc0 0x40 - } - RW_SECTION_B@0x3e8000 0x3e8000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3d7fc0 - RW_FWID_B@0x3e7fc0 0x40 - } - RW_MISC@0x7d0000 0x30000 { - UNIFIED_MRC_CACHE@0x0 0x20000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - } - RW_ELOG(PRESERVE)@0x20000 0x4000 - RW_SHARED@0x24000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x5000 - RW_SPD_CACHE(PRESERVE)@0x2f000 0x1000 - } - # RW_LEGACY needs to be minimum of 1MB - RW_LEGACY(CBFS)@0x800000 0x100000 - WP_RO@0x900000 0x400000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x3fc000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0x3000 - COREBOOT(CBFS)@0x4000 0x3f8000 - } - } - } -} diff --git a/src/mainboard/google/hatch/chromeos-puff-32MiB.fmd b/src/mainboard/google/hatch/chromeos-puff-32MiB.fmd deleted file mode 100644 index 81840b1e60..0000000000 --- a/src/mainboard/google/hatch/chromeos-puff-32MiB.fmd +++ /dev/null @@ -1,48 +0,0 @@ -FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x300000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x2ff000 - } - SI_BIOS@0x300000 0x1d00000 { - # Place RW_LEGACY at the start of BIOS region such that the rest - # of BIOS regions start at 16MiB boundary. Since this is a 32MiB - # SPI flash only the top 16MiB actually gets memory mapped. - RW_LEGACY(CBFS)@0x0 0x1000000 - RW_SECTION_A@0x1000000 0x460000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x44ffc0 - RW_FWID_A@0x45ffc0 0x40 - } - RW_SECTION_B@0x1460000 0x460000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x44ffc0 - RW_FWID_B@0x45ffc0 0x40 - } - RW_MISC@0x18c0000 0x40000 { - UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x20000 - } - RW_ELOG(PRESERVE)@0x30000 0x4000 - RW_SHARED@0x34000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD(PRESERVE)@0x38000 0x2000 - RW_NVRAM(PRESERVE)@0x3a000 0x5000 - RW_SPD_CACHE(PRESERVE)@0x3f000 0x1000 - } - # Make WP_RO region align with SPI vendor - # memory protected range specification. - WP_RO@0x1900000 0x400000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x3fc000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0x3000 - COREBOOT(CBFS)@0x4000 0x3f8000 - } - } - } -} diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 6320d06ecf..489ea2fa59 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -23,9 +23,7 @@ DefinitionBlock( { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> -#if CONFIG(BOARD_GOOGLE_BASEBOARD_HATCH) #include <drivers/intel/gma/acpi/default_brightness_levels.asl> -#endif } } @@ -40,7 +38,6 @@ DefinitionBlock( #include <ec/google/chromeec/acpi/ec.asl> } -#if CONFIG(BOARD_GOOGLE_BASEBOARD_HATCH) /* Dynamic Platform Thermal Framework */ Scope (\_SB) { @@ -49,5 +46,4 @@ DefinitionBlock( /* Include common dptf ASL files */ #include <soc/intel/common/acpi/dptf/dptf.asl> } -#endif } diff --git a/src/mainboard/google/hatch/romstage_spd_cbfs.c b/src/mainboard/google/hatch/romstage.c index eb5153c133..eb5153c133 100644 --- a/src/mainboard/google/hatch/romstage_spd_cbfs.c +++ b/src/mainboard/google/hatch/romstage.c diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c deleted file mode 100644 index 3d84e52448..0000000000 --- a/src/mainboard/google/hatch/romstage_spd_smbus.c +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/variants.h> -#include <console/console.h> -#include <soc/cnl_memcfg_init.h> -#include <soc/romstage.h> -#include <spd_bin.h> -#include <spd_cache.h> - -void mainboard_memory_init_params(FSPM_UPD *memupd) -{ - struct cnl_mb_cfg memcfg; - variant_memory_params(&memcfg); - - /* Read spd block to get memory config */ - struct spd_block blk = { - .addr_map = { 0x50, 0x52, }, - }; - - uint8_t *spd_cache; - size_t spd_cache_sz; - bool need_update_cache = false; - bool dimm_changed = true; - - /* load spd cache from RW_SPD_CACHE */ - if (load_spd_cache(&spd_cache, &spd_cache_sz) == CB_SUCCESS) { - if (!spd_cache_is_valid(spd_cache, spd_cache_sz)) { - printk(BIOS_WARNING, "Invalid SPD cache\n"); - } else { - dimm_changed = check_if_dimm_changed(spd_cache, &blk); - if (dimm_changed && memupd->FspmArchUpd.NvsBufferPtr != 0) { - /* Set mrc_cache as invalid */ - printk(BIOS_INFO, "Set mrc_cache as invalid\n"); - memupd->FspmArchUpd.NvsBufferPtr = 0; - } - } - need_update_cache = true; - } - - if (!dimm_changed) { - spd_fill_from_cache(spd_cache, &blk); - } else { - /* Access memory info through SMBUS. */ - get_spd_smbus(&blk); - - if (need_update_cache && update_spd_cache(&blk) == CB_ERR) - printk(BIOS_WARNING, "update SPD cache failed\n"); - } - - if (blk.spd_array[0] == NULL) { - memcfg.spd[0].read_type = NOT_EXISTING; - } else { - memcfg.spd[0].read_type = READ_SPD_MEMPTR; - memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_len = blk.len; - memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[0]; - } - - memcfg.spd[1].read_type = NOT_EXISTING; - - if (blk.spd_array[1] == NULL) { - memcfg.spd[2].read_type = NOT_EXISTING; - } else { - memcfg.spd[2].read_type = READ_SPD_MEMPTR; - memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_len = blk.len; - memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[1]; - } - - memcfg.spd[3].read_type = NOT_EXISTING; - dump_spd_info(&blk); - - /* set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. */ - memcfg.vref_ca_config = 2; - memcfg.dq_pins_interleaved = 1; - - cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); -} diff --git a/src/mainboard/google/hatch/variants/ambassador/Makefile.inc b/src/mainboard/google/hatch/variants/ambassador/Makefile.inc deleted file mode 100644 index 3b5b7d000d..0000000000 --- a/src/mainboard/google/hatch/variants/ambassador/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ramstage-y += gpio.c -bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/ambassador/gpio.c b/src/mainboard/google/hatch/variants/ambassador/gpio.c deleted file mode 100644 index 996edc4fc7..0000000000 --- a/src/mainboard/google/hatch/variants/ambassador/gpio.c +++ /dev/null @@ -1,117 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <commonlib/helpers.h> - -static const struct pad_config gpio_table[] = { - /* A16 : SD_OC_ODL */ - PAD_CFG_GPI(GPP_A16, NONE, DEEP), - /* A18 : LAN_PE_ISOLATE_ODL */ - PAD_CFG_GPO(GPP_A18, 1, DEEP), - /* A23 : M2_WLAN_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), - - /* B5 : LAN_CLKREQ_ODL */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), - - /* C0 : SMBCLK */ - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), - /* C1 : SMBDATA */ - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - /* C6: M2_WLAN_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), - /* C7 : LAN_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), - /* C10 : PCH_PCON_RST_ODL */ - PAD_CFG_GPO(GPP_C10, 1, DEEP), - /* C11 : PCH_PCON_PDB_ODL */ - PAD_CFG_GPO(GPP_C11, 1, DEEP), - /* C15 : WLAN_OFF_L */ - PAD_CFG_GPO(GPP_C15, 1, DEEP), - - /* E2 : EN_PP_MST_OD */ - PAD_CFG_GPO(GPP_E2, 1, DEEP), - /* E9 : USB_A0_OC_ODL */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - /* E10 : USB_A1_OC_ODL */ - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), - - /* F11 : EMMC_CMD */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), - /* F12 : EMMC_DATA0 */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), - /* F13 : EMMC_DATA1 */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), - /* F14 : EMMC_DATA2 */ - PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), - /* F15 : EMMC_DATA3 */ - PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), - /* F16 : EMMC_DATA4 */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), - /* F17 : EMMC_DATA5 */ - PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), - /* F18 : EMMC_DATA6 */ - PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), - /* F19 : EMMC_DATA7 */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - /* F20 : EMMC_RCLK */ - PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), - /* F21 : EMMC_CLK */ - PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), - /* F22 : EMMC_RST_L */ - PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), - - /* H4: PCH_I2C_PCON_SDA */ - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* H5: PCH_I2C_PCON_SCL */ - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* H22 : PWM_PP3300_BIOZZER */ - PAD_CFG_GPO(GPP_H22, 0, DEEP), -}; - -const struct pad_config *override_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* B14 : GPP_B14_STRAP */ - PAD_NC(GPP_B14, NONE), - /* B22 : GPP_B22_STRAP */ - PAD_NC(GPP_B22, NONE), - /* E19 : GPP_E19_STRAP */ - PAD_NC(GPP_E19, NONE), - /* E21 : GPP_E21_STRAP */ - PAD_NC(GPP_E21, NONE), - /* B15 : H1_SLAVE_SPI_CS_L */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* B16 : H1_SLAVE_SPI_CLK */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* B17 : H1_SLAVE_SPI_MISO_R */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* B18 : H1_SLAVE_SPI_MOSI_R */ - PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* C14 : BT_DISABLE_L */ - PAD_CFG_GPO(GPP_C14, 0, DEEP), - /* PCH_WP_OD */ - PAD_CFG_GPI(GPP_C20, NONE, DEEP), - /* C21 : H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), - /* C22 : EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_C22, NONE, DEEP), - /* C23 : WLAN_PE_RST# */ - PAD_CFG_GPO(GPP_C23, 1, DEEP), - /* E1 : M2_SSD_PEDET */ - PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), - /* E5 : SATA_DEVSLP1 */ - PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), -}; - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} diff --git a/src/mainboard/google/hatch/variants/ambassador/include/variant/ec.h b/src/mainboard/google/hatch/variants/ambassador/include/variant/ec.h deleted file mode 100644 index 59fb3783c5..0000000000 --- a/src/mainboard/google/hatch/variants/ambassador/include/variant/ec.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_EC_H -#define VARIANT_EC_H - -#include <puff/ec.h> - -#endif diff --git a/src/mainboard/google/hatch/variants/ambassador/include/variant/gpio.h b/src/mainboard/google/hatch/variants/ambassador/include/variant/gpio.h deleted file mode 100644 index 79a141008f..0000000000 --- a/src/mainboard/google/hatch/variants/ambassador/include/variant/gpio.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include <baseboard/gpio.h> - -#endif diff --git a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb deleted file mode 100644 index b4f3609ba0..0000000000 --- a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb +++ /dev/null @@ -1,488 +0,0 @@ -chip soc/intel/cannonlake - register "tcc_offset" = "5" # TCC of 95C - - register "power_limits_config" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 51, - }" - - # Auto-switch between X4 NVMe and X2 NVMe. - register "TetonGlacierMode" = "1" - - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - [PchSerialIoIndexSPI0] = PchSerialIoPci, - [PchSerialIoIndexSPI1] = PchSerialIoPci, - [PchSerialIoIndexSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoSkipInit, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - - # USB configuration - register "usb2_ports[0]" = "{ - .enable = 1, - .ocpin = OC2, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_11P25MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 2 - register "usb2_ports[1]" = "{ - .enable = 1, - .ocpin = OC1, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 1 - register "usb2_ports[2]" = "{ - .enable = 1, - .ocpin = OC3, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 3 - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port - register "usb2_ports[4]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 4 - register "usb2_ports[5]" = "{ - .enable = 1, - .ocpin = OC0, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A port 0 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" - register "usb2_ports[9]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # BT - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 - - # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ - USB_PORT_WAKE_ENABLE(6)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ - USB_PORT_WAKE_ENABLE(6)" - - # Enable eMMC HS400 - register "ScsEmmcHs400Enabled" = "1" - - # EMMC Tx CMD Delay - # Refer to EDS-Vol2-14.3.7. - # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" - - # EMMC TX DATA Delay 1 - # Refer to EDS-Vol2-14.3.8. - # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. - # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" - - # EMMC TX DATA Delay 2 - # Refer to EDS-Vol2-14.3.9. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. - # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" - - # EMMC RX CMD/DATA Delay 1 - # Refer to EDS-Vol2-14.3.10. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. - # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" - - # EMMC RX CMD/DATA Delay 2 - # Refer to EDS-Vol2-14.3.12. - # [17:16] stands for Rx Clock before Output Buffer, - # 00: Rx clock after output buffer, - # 01: Rx clock before output buffer, - # 10: Automatic selection based on working mode. - # 11: Reserved - # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" - - # EMMC Rx Strobe Delay - # Refer to EDS-Vol2-14.3.11. - # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. - # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" - - # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. - register "PchHdaAudioLinkSsp1" = "0" - register "PchHdaAudioLinkDmic0" = "0" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| I2C0 | RFU | - #| I2C2 | PS175 | - #| I2C3 | MST | - #| I2C4 | Audio | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 0, - .fall_time_ns = 0, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - .i2c[4] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - }" - - # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" - # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" - # Uses CLK SRC 0 - register "PcieClkSrcUsage[0]" = "6" - register "PcieClkSrcClkReq[0]" = "0" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "vSD3_CD_B" - - # SATA port 1 Gen3 Strength - # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB - register "sata_port[1].TxGen3DeEmphEnable" = "1" - register "sata_port[1].TxGen3DeEmph" = "0x20" - - device domain 0 on - device pci 04.0 on - chip drivers/intel/dptf - ## Active Policy - register "policies.active[0]" = "{.target=DPTF_CPU, - .thresholds={TEMP_PCT(94, 0),}}" - register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, - .thresholds={TEMP_PCT(72, 90), - TEMP_PCT(68, 80), - TEMP_PCT(64, 70), - TEMP_PCT(58, 60), - TEMP_PCT(51, 50), - TEMP_PCT(42, 40), - TEMP_PCT(35, 30),}}" - - ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000)" - register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000)" - - ## Critical Policy - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)" - register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN)" - - ## Power Limits Control - # PL1 is fixed at 15W, avg over 28-32s interval - # 15-51W PL2 in 1000mW increments, avg over 28-32s interval - register "controls.power_limits.pl1" = "{ - .min_power = 15000, - .max_power = 15000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200,}" - register "controls.power_limits.pl2" = "{ - .min_power = 25000, - .max_power = 51000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 1000,}" - - ## Charger Performance Control (Control, mA) - register "controls.charger_perf[0]" = "{ 255, 1700 }" - register "controls.charger_perf[1]" = "{ 24, 1500 }" - register "controls.charger_perf[2]" = "{ 16, 1000 }" - register "controls.charger_perf[3]" = "{ 8, 500 }" - - ## Fan Performance Control (Percent, Speed, Noise, Power) - register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" - register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" - register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" - register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" - register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" - register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" - register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" - register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" - register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" - register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" - - # Fan options - register "options.fan.fine_grained_control" = "1" - register "options.fan.step_size" = "2" - - device generic 0 on end - end - end # DPTF 0x1903 - device pci 14.0 on - chip drivers/usb/acpi - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Left"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 3)" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Right"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Right"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 2.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Middle"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Left"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 2.5 on end - end - chip drivers/usb/acpi - device usb 2.6 off end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Left"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Right"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Right"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 3)" - device usb 3.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Left"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 3.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Middle"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 3.5 on end - end - end - end - end # USB xHCI - device pci 15.0 off - # RFU - Reserved for Future Use. - end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 on - chip drivers/i2c/generic - register "hid" = ""1AF80175"" - register "name" = ""PS17"" - register "desc" = ""Parade PS175"" - device i2c 4a on end - end - end # I2C #2, PCON PS175. - device pci 15.3 on - chip drivers/i2c/generic - register "hid" = ""10EC2142"" - register "name" = ""RTD2"" - register "desc" = ""Realtek RTD2142"" - device i2c 4a on end - end - end # I2C #3, Realtek RTD2142. - device pci 16.0 on end # Management Engine Interface 1 - device pci 19.0 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" - register "property_count" = "1" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on end - end - end #I2C #4 - device pci 1a.0 on end # eMMC - device pci 1c.6 on - chip drivers/net - register "customized_leds" = "0x05af" - register "wake" = "GPE0_DW1_07" # GPP_C7 - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" - register "stop_delay_ms" = "12" # NIC needs time to quiesce - register "stop_off_delay_ms" = "1" - register "has_power_resource" = "1" - register "device_index" = "0" - device pci 00.0 on end - end - register "PcieRpSlotImplemented[6]" = "1" - end # RTL8111H Ethernet NIC - device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) - register "PcieRpSlotImplemented[10]" = "1" - end - device pci 1e.3 off end # GSPI #1 - end - - # VR Settings Configuration for 4 Domains - #+----------------+-------+-------+-------+-------+ - #| Domain/Setting | SA | IA | GTUS | GTS | - #+----------------+-------+-------+-------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | - #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | - #+----------------+-------+-------+-------+-------+ - #Note: IccMax settings are moved to SoC code - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 1004, - .dc_loadline = 1004, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 181, - .dc_loadline = 181, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 319, - .dc_loadline = 319, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 319, - .dc_loadline = 319, - }" - -end diff --git a/src/mainboard/google/hatch/variants/baseboard/Makefile.inc b/src/mainboard/google/hatch/variants/baseboard/Makefile.inc index 69f9322fb5..c0514376ac 100644 --- a/src/mainboard/google/hatch/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/hatch/variants/baseboard/Makefile.inc @@ -6,7 +6,6 @@ romstage-y += gpio.c romstage-y += memory.c ramstage-y += gpio.c -ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_PUFF) += mainboard.c verstage-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/baseboard/mainboard.c b/src/mainboard/google/hatch/variants/baseboard/mainboard.c deleted file mode 100644 index e0c344064c..0000000000 --- a/src/mainboard/google/hatch/variants/baseboard/mainboard.c +++ /dev/null @@ -1,171 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/variants.h> -#include <bootmode.h> -#include <chip.h> -#include <console/console.h> -#include <delay.h> -#include <device/device.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <ec/google/chromeec/ec.h> -#include <gpio.h> -#include <intelblocks/power_limit.h> -#include <soc/pci_devs.h> -#include <timer.h> - -#define GPIO_HDMI_HPD GPP_E13 -#define GPIO_DP_HPD GPP_E14 - -/* TODO: This can be moved to common directory */ -static void wait_for_hpd(gpio_t gpio, long timeout) -{ - struct stopwatch sw; - - printk(BIOS_INFO, "Waiting for HPD\n"); - stopwatch_init_msecs_expire(&sw, timeout); - while (!gpio_get(gpio)) { - if (stopwatch_expired(&sw)) { - printk(BIOS_WARNING, - "HPD not ready after %ldms. Abort.\n", timeout); - return; - } - mdelay(200); - } - printk(BIOS_INFO, "HPD ready after %lld ms\n", - stopwatch_duration_msecs(&sw)); -} - -/* - * For type-C chargers, set PL2 to 97% of max power to account for - * cable loss and FET Rdson loss in the path from the source. - */ -#define SET_PSYSPL2(w) (97 * (w) / 100) -#define PUFF_U22_PL2 (35) -#define PUFF_U62_U42_PL2 (51) -#define PUFF_CELERON_PENTIUM_PSYSPL2 (65) -#define PUFF_CORE_CPU_PSYSPL2 (90) -#define PUFF_MAX_TIME_WINDOW 6 -#define PUFF_MIN_DUTYCYCLE 4 - -/* - * mainboard_set_power_limits - * - * Set Pl2 and SysPl2 values based on detected charger. - * Values are defined below but we use U22 value for all SKUs for now. - * definitions: - * x = no value entered. Use default value in parenthesis. - * will set 0 to anything that shouldn't be set. - * n = max value of power adapter. - * +-------------+-----+---------+-----------+-------+ - * | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 | - * +-------------+-----+---------+-----------+-------+ - * | i7 U42 | 51 | 90 | x(.85PL4) | x(82) | - * | i3 U22 | 35 | 65 | x(.85PL4) | x(51) | - * +-------------+-----+---------+-----------+-------+ - * For USB C charger: - * +-------------+-----------------+---------+---------+-------+ - * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 | - * +-------------+-----+-----------+---------+---------+-------+ - * | n | min(0.97n, PL2) | 0.97n | 0.97n | 0.97n | - * +-------------+-----+-----------+---------+---------+-------+ - */ - -/* - * Psys_pmax considerations - * - * Given the hardware design in puff, the serial shunt resistor is 0.01ohm. - * The full scale of hardware PSYS signal 0.8v maps to system current 9.6A - * instead of real system power. The equation is shown below: - * PSYS = 0.8v = (0.01ohm x Iinput) x 50 (INA213, gain 50V/V) x 15k/(15k + 75k) - * Hence, Iinput (Amps) = 9.6A - * Since there is no voltage information from PSYS, different voltage input - * would map to different Psys_pmax settings: - * For Type-C 15V, the Psys_pmax sholud be 15v x 9.6A = 144W - * For Type-C 20V, the Psys_pmax should be 20v x 9.6A = 192W - * For a barral jack, the Psys_pmax should be 19v x 9.6A = 182.4W - */ -#define PSYS_IMAX 9600 -#define BJ_VOLTS_MV 19000 - -static void mainboard_set_power_limits(struct soc_power_limits_config *conf) -{ - enum usb_chg_type type; - u32 watts; - u16 volts_mv, current_ma; - u32 psyspl2 = PUFF_CELERON_PENTIUM_PSYSPL2; // default BJ value - u32 pl2 = PUFF_U22_PL2; // default PL2 for U22 - int rv = google_chromeec_get_usb_pd_power_info(&type, ¤t_ma, &volts_mv); - - struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); - u16 mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; - dev = pcidev_path_on_root(SA_DEVFN_IGD); - u16 igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; - - /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/ - conf->tdp_psyspl3 = 0; - conf->tdp_pl4 = 0; - - if (rv == 0 && type == USB_CHG_TYPE_PD) { - /* Detected USB-PD. Base on max value of adapter */ - watts = ((u32)current_ma * volts_mv) / 1000000; - /* set psyspl2 to 90% of adapter rating */ - psyspl2 = SET_PSYSPL2(watts); - - /* Limit PL2 if the adapter is with lower capability */ - if (mch_id == PCI_DID_INTEL_CML_ULT || - mch_id == PCI_DID_INTEL_CML_ULT_6_2) - pl2 = (psyspl2 > PUFF_U62_U42_PL2) ? PUFF_U62_U42_PL2 : psyspl2; - else - pl2 = (psyspl2 > PUFF_U22_PL2) ? PUFF_U22_PL2 : psyspl2; - - conf->tdp_psyspl3 = psyspl2; - /* set max possible time window */ - conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW; - /* set minimum duty cycle */ - conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE; - /* No data about an arbitrary Type-C adapter, set pl4 conservatively. */ - conf->tdp_pl4 = psyspl2; - } else { - /* - * Input type is barrel jack, from the SKU matrix: - * 1. i3/i5/i7 SKUs use 90W BJ - * 2. Celeron and Pentium use 65W BJ (default) - */ - volts_mv = BJ_VOLTS_MV; - /* Use IGD ID to check if CPU is Core SKUs */ - if (igd_id != PCI_DID_INTEL_CML_GT1_ULT_1 && - igd_id != PCI_DID_INTEL_CML_GT2_ULT_5) { - psyspl2 = PUFF_CORE_CPU_PSYSPL2; - if (mch_id == PCI_DID_INTEL_CML_ULT || - mch_id == PCI_DID_INTEL_CML_ULT_6_2) - pl2 = PUFF_U62_U42_PL2; - } - } - /* voltage unit is milliVolts and current is in milliAmps */ - conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000); - - conf->tdp_pl2_override = pl2; - conf->tdp_psyspl2 = psyspl2; -} - -void variant_ramstage_init(void) -{ - static const long display_timeout_ms = 3000; - struct soc_power_limits_config *soc_config; - config_t *conf = config_of_soc(); - - /* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */ - gpio_input(GPIO_HDMI_HPD); - gpio_input(GPIO_DP_HPD); - if (display_init_required() - && !gpio_get(GPIO_HDMI_HPD) - && !gpio_get(GPIO_DP_HPD)) { - /* This has to be done before FSP-S runs. */ - if (google_chromeec_wait_for_displayport(display_timeout_ms)) - wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); - } - /* Psys_pmax needs to be setup before FSP-S */ - soc_config = &conf->power_limits_config; - mainboard_set_power_limits(soc_config); -} diff --git a/src/mainboard/google/hatch/variants/dooly/Makefile.inc b/src/mainboard/google/hatch/variants/dooly/Makefile.inc deleted file mode 100644 index 3b5b7d000d..0000000000 --- a/src/mainboard/google/hatch/variants/dooly/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ramstage-y += gpio.c -bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/dooly/data.vbt b/src/mainboard/google/hatch/variants/dooly/data.vbt Binary files differdeleted file mode 100644 index 42fc269659..0000000000 --- a/src/mainboard/google/hatch/variants/dooly/data.vbt +++ /dev/null diff --git a/src/mainboard/google/hatch/variants/dooly/gpio.c b/src/mainboard/google/hatch/variants/dooly/gpio.c deleted file mode 100644 index 37cd08cdae..0000000000 --- a/src/mainboard/google/hatch/variants/dooly/gpio.c +++ /dev/null @@ -1,154 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <commonlib/helpers.h> - -static const struct pad_config gpio_table[] = { - /* A17 : SD_VDD1_PWR_EN */ - PAD_NC(GPP_A17, NONE), - /* A18 : GPP_A18 */ - PAD_NC(GPP_A18, NONE), - /* A19 : GPP_A19 */ - PAD_NC(GPP_A19, NONE), - /* A20 : TOUCH_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_A20, NONE, PLTRST, LEVEL, INVERT), - /* A21 : FPMCU_PCH_BOOT0 */ - PAD_NC(GPP_A21, NONE), - /* A22 : FPMCU_PCH_INT_L */ - PAD_NC(GPP_A22, NONE), - /* A23 : M2_WLAN_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), - - /* C0 : SMBCLK */ - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), - /* C1 : SMBDATA */ - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - /* C3 : GPP_C3 */ - PAD_NC(GPP_C3, NONE), - /* C4 : GPP_C4 */ - PAD_NC(GPP_C4, NONE), - /* C6: M2_WLAN_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), - /* C7 : LAN_WAKE_ODL */ - PAD_NC(GPP_C7, NONE), - /* C11 : GPP_C11 */ - PAD_NC(GPP_C11, NONE), - /* C15 : WLAN_OFF_L */ - PAD_CFG_GPO(GPP_C15, 1, DEEP), - /* C18 : GPP_C18 */ - PAD_NC(GPP_C18, NONE), - /* C19 : GPP_C19 */ - PAD_NC(GPP_C19, NONE), - - /* D16 : DMIC_ON_OFF MIC_SWITCH_L */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_D16, NONE, DEEP), - - /* E2 : EN_PP_MST_OD */ - PAD_CFG_GPO(GPP_E2, 1, DEEP), - - /* F0 : GPP_F0 */ - PAD_NC(GPP_F0, NONE), - /* F1 : GPP_F1 */ - PAD_NC(GPP_F1, NONE), - /* F8 : GPP_F8 */ - PAD_NC(GPP_F8, NONE), - /* F9 : GPP_F9 */ - PAD_NC(GPP_F9, NONE), - /* F11 : EMMC_CMD */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), - /* F12 : EMMC_DATA0 */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), - /* F13 : EMMC_DATA1 */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), - /* F14 : EMMC_DATA2 */ - PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), - /* F15 : EMMC_DATA3 */ - PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), - /* F16 : EMMC_DATA4 */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), - /* F17 : EMMC_DATA5 */ - PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), - /* F18 : EMMC_DATA6 */ - PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), - /* F19 : EMMC_DATA7 */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - /* F20 : EMMC_RCLK */ - PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), - /* F21 : EMMC_CLK */ - PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), - /* F22 : EMMC_RST_L */ - PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), - - /* G0 : SD_CMD */ - PAD_NC(GPP_G0, NONE), - /* G1 : SD_DATA0 */ - PAD_NC(GPP_G1, NONE), - /* G2 : SD_DATA1 */ - PAD_NC(GPP_G2, NONE), - /* G3 : SD_DATA2 */ - PAD_NC(GPP_G3, NONE), - /* G4 : SD_DATA3 */ - PAD_NC(GPP_G4, NONE), - /* G5 : SD_CD */ - PAD_NC(GPP_G5, NONE), - /* G6 : SD_CLK */ - PAD_NC(GPP_G6, NONE), - - /* H3 : SPK_AMP_ON */ - PAD_CFG_GPO(GPP_H3, 1, DEEP), - /* H4: LVDS_SDA */ - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* H5: LVDS_SDL */ - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* H6 : PCH_I2C_TOUCH_SDA */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), - /* H7 : PCH_I2C_TOUCH_SDL */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), -}; - -const struct pad_config *override_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* B14 : GPP_B14_STRAP */ - PAD_NC(GPP_B14, NONE), - /* B22 : GPP_B22_STRAP */ - PAD_NC(GPP_B22, NONE), - /* E19 : GPP_E19_STRAP */ - PAD_NC(GPP_E19, NONE), - /* E21 : GPP_E21_STRAP */ - PAD_NC(GPP_E21, NONE), - /* B15 : H1_SLAVE_SPI_CS_L */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* B16 : H1_SLAVE_SPI_CLK */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* B17 : H1_SLAVE_SPI_MISO_R */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* B18 : H1_SLAVE_SPI_MOSI_R */ - PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* C14 : BT_DISABLE_L */ - PAD_CFG_GPO(GPP_C14, 0, DEEP), - /* PCH_WP_OD */ - PAD_CFG_GPI(GPP_C20, NONE, DEEP), - /* C21 : H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), - /* C22 : EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_C22, NONE, DEEP), - /* C23 : WLAN_PE_RST# */ - PAD_CFG_GPO(GPP_C23, 1, DEEP), - /* E1 : M2_SSD_PEDET */ - PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), - /* E5 : SATA_DEVSLP1 */ - PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), -}; - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} diff --git a/src/mainboard/google/hatch/variants/dooly/include/variant/ec.h b/src/mainboard/google/hatch/variants/dooly/include/variant/ec.h deleted file mode 100644 index 7d280c6edf..0000000000 --- a/src/mainboard/google/hatch/variants/dooly/include/variant/ec.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_EC_H -#define VARIANT_EC_H - -#include <puff/ec.h> - -/* Enable EC backed ALS device in ACPI */ -#define EC_ENABLE_ALS_DEVICE - -#endif diff --git a/src/mainboard/google/hatch/variants/dooly/include/variant/gpio.h b/src/mainboard/google/hatch/variants/dooly/include/variant/gpio.h deleted file mode 100644 index 79a141008f..0000000000 --- a/src/mainboard/google/hatch/variants/dooly/include/variant/gpio.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include <baseboard/gpio.h> - -#endif diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb deleted file mode 100644 index 8533f024ea..0000000000 --- a/src/mainboard/google/hatch/variants/dooly/overridetree.cb +++ /dev/null @@ -1,470 +0,0 @@ -fw_config - field AUDIO_CODEC_SOURCE 8 10 - option AUDIO_CODEC_UNPROVISIONED 0 - option AUDIO_CODEC_ALC5682 1 - option AUDIO_CODEC_ALC5682I_VS 2 - end -end - -chip soc/intel/cannonlake - - register "power_limits_config" = "{ - .tdp_pl1_override = 25, - .tdp_pl2_override = 49, - }" - - # Auto-switch between X4 NVMe and X2 NVMe. - register "TetonGlacierMode" = "1" - - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - [PchSerialIoIndexSPI0] = PchSerialIoPci, - [PchSerialIoIndexSPI1] = PchSerialIoPci, - [PchSerialIoIndexSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoSkipInit, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - - # USB configuration - register "usb2_ports[0]" = "{ - .enable = 1, - .ocpin = OC2, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_11P25MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 0 - register "usb2_ports[1]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-C Port 0 - register "usb2_ports[2]" = "{ - .enable = 1, - .ocpin = OC3, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 1 - register "usb2_ports[3]" = "USB2_PORT_EMPTY" - register "usb2_ports[4]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-C Port 1 - register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # USB cam - register "usb2_ports[6]" = "USB2_PORT_EMPTY" - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port 1 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port 0 - register "usb3_ports[4]" = "USB3_PORT_EMPTY" - register "usb3_ports[5]" = "USB3_PORT_EMPTY" - - # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(3)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2)" - - # Enable eMMC HS400 - register "ScsEmmcHs400Enabled" = "1" - - # EMMC Tx CMD Delay - # Refer to EDS-Vol2-14.3.7. - # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" - - # EMMC TX DATA Delay 1 - # Refer to EDS-Vol2-14.3.8. - # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. - # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" - - # EMMC TX DATA Delay 2 - # Refer to EDS-Vol2-14.3.9. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. - # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" - - # EMMC RX CMD/DATA Delay 1 - # Refer to EDS-Vol2-14.3.10. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. - # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" - - # EMMC RX CMD/DATA Delay 2 - # Refer to EDS-Vol2-14.3.12. - # [17:16] stands for Rx Clock before Output Buffer, - # 00: Rx clock after output buffer, - # 01: Rx clock before output buffer, - # 10: Automatic selection based on working mode. - # 11: Reserved - # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" - - # EMMC Rx Strobe Delay - # Refer to EDS-Vol2-14.3.11. - # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. - # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| I2C0 | ALC 1015 | - #| I2C2 | Lvds | - #| I2C3 | Touchscreen | - #| I2C4 | RT5682 | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - .i2c[4] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - }" - - # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" - # Uses CLK SRC 0 - register "PcieClkSrcUsage[0]" = "6" - register "PcieClkSrcClkReq[0]" = "0" - - # SATA port 1 Gen3 Strength - # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB - register "sata_port[1].TxGen3DeEmphEnable" = "1" - register "sata_port[1].TxGen3DeEmph" = "0x20" - - device domain 0 on - device pci 04.0 on - chip drivers/intel/dptf - ## Active Policy - register "policies.active[0]" = "{.target=DPTF_CPU, - .thresholds={TEMP_PCT(90, 0),}}" - register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, - .thresholds={TEMP_PCT(75, 60), - TEMP_PCT(65, 50), - TEMP_PCT(45, 40), - TEMP_PCT(30, 30),}}" - - ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 85, 60000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 76, 60000)" - - ## Critical Policy - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)" - - ## Power Limits Control - # 15-25W PL1 in 1000mW increments, avg over 28-32s interval - # 40-49W PL2 in 1000mW increments, avg over 28-32s interval - register "controls.power_limits.pl1" = "{ - .min_power = 15000, - .max_power = 25000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 1000,}" - register "controls.power_limits.pl2" = "{ - .min_power = 40000, - .max_power = 49000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 1000,}" - - ## Fan Performance Control (Percent, Speed, Noise, Power) - register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" - register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" - register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" - register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" - register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" - register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" - register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" - register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" - register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" - register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" - - # Fan options - register "options.fan.fine_grained_control" = "1" - register "options.fan.step_size" = "2" - - device generic 0 on end - end - end # DPTF 0x1903 - device pci 14.0 on - chip drivers/usb/acpi - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Port 0"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port 0"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Port 1"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 2.2 on end - end - chip drivers/usb/acpi - device usb 2.3 off end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port 1"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 2)" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""Camera"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.5 on end - end - chip drivers/usb/acpi - device usb 2.6 off end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Port 0"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Port 1"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port 1"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 2)" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port 0"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" - device usb 3.3 on end - end - chip drivers/usb/acpi - device usb 3.4 off end - end - chip drivers/usb/acpi - device usb 3.5 off end - end - end - end - end # USB xHCI - device pci 14.5 off end # SDCard - device pci 15.0 on - chip drivers/i2c/generic - register "hid" = ""10EC1015"" - register "desc" = ""Realtek SPK AMP L"" - register "uid" = "0" - device i2c 28 on end - end - chip drivers/i2c/generic - register "hid" = ""10EC1015"" - register "desc" = ""Realtek SPK AMP R"" - register "uid" = "1" - device i2c 29 on end - end - end # I2C #0 ALC1015 - device pci 15.1 off end # I2C #1 - device pci 15.2 on end # I2C #2 LVDS - device pci 15.3 on - chip drivers/i2c/hid - register "generic.hid" = ""WDHT2002"" - register "generic.desc" = ""WDT Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A20_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "100" - register "generic.wake" = "GPE0_DW0_20" - register "generic.has_power_resource" = "1" - register "generic.disable_gpio_export_in_crs" = "1" - register "hid_desc_reg_offset" = "0x20" - device i2c 2c on end - end - end # I2C #3 Touchscreen - device pci 16.0 on end # Management Engine Interface 1 - device pci 19.0 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" - register "property_count" = "1" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on - probe AUDIO_CODEC_SOURCE AUDIO_CODEC_UNPROVISIONED - probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682 - end - end - chip drivers/i2c/generic - register "hid" = ""RTL5682"" - register "name" = ""RT58"" - register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" - register "property_count" = "1" - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on - probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS - end - end - chip drivers/generic/gpio_keys - register "name" = ""MUTE"" - register "label" = ""mic_mute_switch"" - register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D16)" - register "key.wakeup_route" = "WAKEUP_ROUTE_DISABLED" - register "key.dev_name" = ""MMSW"" - register "key.linux_code" = "SW_MUTE_DEVICE" - register "key.linux_input_type" = "EV_SW" - register "key.label" = ""mic_mute_switch_key"" - device generic 0 on end - end - end #I2C #4 - device pci 1a.0 on end # eMMC - device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) - register "PcieRpSlotImplemented[10]" = "1" - end - device pci 1e.3 off end # GSPI #1 - end - - # VR Settings Configuration for 4 Domains - #+----------------+-------+-------+-------+-------+ - #| Domain/Setting | SA | IA | GTUS | GTS | - #+----------------+-------+-------+-------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | - #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | - #+----------------+-------+-------+-------+-------+ - #Note: IccMax settings are moved to SoC code - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 1004, - .dc_loadline = 1004, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 181, - .dc_loadline = 181, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 319, - .dc_loadline = 319, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 319, - .dc_loadline = 319, - }" - -end diff --git a/src/mainboard/google/hatch/variants/duffy/Makefile.inc b/src/mainboard/google/hatch/variants/duffy/Makefile.inc deleted file mode 100644 index 3b5b7d000d..0000000000 --- a/src/mainboard/google/hatch/variants/duffy/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ramstage-y += gpio.c -bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/duffy/data.vbt b/src/mainboard/google/hatch/variants/duffy/data.vbt Binary files differdeleted file mode 100644 index cda1c25d7d..0000000000 --- a/src/mainboard/google/hatch/variants/duffy/data.vbt +++ /dev/null diff --git a/src/mainboard/google/hatch/variants/duffy/gpio.c b/src/mainboard/google/hatch/variants/duffy/gpio.c deleted file mode 100644 index 996edc4fc7..0000000000 --- a/src/mainboard/google/hatch/variants/duffy/gpio.c +++ /dev/null @@ -1,117 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <commonlib/helpers.h> - -static const struct pad_config gpio_table[] = { - /* A16 : SD_OC_ODL */ - PAD_CFG_GPI(GPP_A16, NONE, DEEP), - /* A18 : LAN_PE_ISOLATE_ODL */ - PAD_CFG_GPO(GPP_A18, 1, DEEP), - /* A23 : M2_WLAN_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), - - /* B5 : LAN_CLKREQ_ODL */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), - - /* C0 : SMBCLK */ - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), - /* C1 : SMBDATA */ - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - /* C6: M2_WLAN_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), - /* C7 : LAN_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), - /* C10 : PCH_PCON_RST_ODL */ - PAD_CFG_GPO(GPP_C10, 1, DEEP), - /* C11 : PCH_PCON_PDB_ODL */ - PAD_CFG_GPO(GPP_C11, 1, DEEP), - /* C15 : WLAN_OFF_L */ - PAD_CFG_GPO(GPP_C15, 1, DEEP), - - /* E2 : EN_PP_MST_OD */ - PAD_CFG_GPO(GPP_E2, 1, DEEP), - /* E9 : USB_A0_OC_ODL */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - /* E10 : USB_A1_OC_ODL */ - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), - - /* F11 : EMMC_CMD */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), - /* F12 : EMMC_DATA0 */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), - /* F13 : EMMC_DATA1 */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), - /* F14 : EMMC_DATA2 */ - PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), - /* F15 : EMMC_DATA3 */ - PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), - /* F16 : EMMC_DATA4 */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), - /* F17 : EMMC_DATA5 */ - PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), - /* F18 : EMMC_DATA6 */ - PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), - /* F19 : EMMC_DATA7 */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - /* F20 : EMMC_RCLK */ - PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), - /* F21 : EMMC_CLK */ - PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), - /* F22 : EMMC_RST_L */ - PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), - - /* H4: PCH_I2C_PCON_SDA */ - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* H5: PCH_I2C_PCON_SCL */ - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* H22 : PWM_PP3300_BIOZZER */ - PAD_CFG_GPO(GPP_H22, 0, DEEP), -}; - -const struct pad_config *override_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* B14 : GPP_B14_STRAP */ - PAD_NC(GPP_B14, NONE), - /* B22 : GPP_B22_STRAP */ - PAD_NC(GPP_B22, NONE), - /* E19 : GPP_E19_STRAP */ - PAD_NC(GPP_E19, NONE), - /* E21 : GPP_E21_STRAP */ - PAD_NC(GPP_E21, NONE), - /* B15 : H1_SLAVE_SPI_CS_L */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* B16 : H1_SLAVE_SPI_CLK */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* B17 : H1_SLAVE_SPI_MISO_R */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* B18 : H1_SLAVE_SPI_MOSI_R */ - PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* C14 : BT_DISABLE_L */ - PAD_CFG_GPO(GPP_C14, 0, DEEP), - /* PCH_WP_OD */ - PAD_CFG_GPI(GPP_C20, NONE, DEEP), - /* C21 : H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), - /* C22 : EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_C22, NONE, DEEP), - /* C23 : WLAN_PE_RST# */ - PAD_CFG_GPO(GPP_C23, 1, DEEP), - /* E1 : M2_SSD_PEDET */ - PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), - /* E5 : SATA_DEVSLP1 */ - PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), -}; - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} diff --git a/src/mainboard/google/hatch/variants/duffy/include/variant/ec.h b/src/mainboard/google/hatch/variants/duffy/include/variant/ec.h deleted file mode 100644 index 59fb3783c5..0000000000 --- a/src/mainboard/google/hatch/variants/duffy/include/variant/ec.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_EC_H -#define VARIANT_EC_H - -#include <puff/ec.h> - -#endif diff --git a/src/mainboard/google/hatch/variants/duffy/include/variant/gpio.h b/src/mainboard/google/hatch/variants/duffy/include/variant/gpio.h deleted file mode 100644 index 79a141008f..0000000000 --- a/src/mainboard/google/hatch/variants/duffy/include/variant/gpio.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include <baseboard/gpio.h> - -#endif diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb deleted file mode 100644 index 25778f92cb..0000000000 --- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb +++ /dev/null @@ -1,547 +0,0 @@ -chip soc/intel/cannonlake - register "tcc_offset" = "5" # TCC of 95C - - register "power_limits_config" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 51, - }" - - # Auto-switch between X4 NVMe and X2 NVMe. - register "TetonGlacierMode" = "1" - - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - [PchSerialIoIndexSPI0] = PchSerialIoPci, - [PchSerialIoIndexSPI1] = PchSerialIoPci, - [PchSerialIoIndexSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoSkipInit, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - - # USB configuration - register "usb2_ports[0]" = "{ - .enable = 1, - .ocpin = OC2, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_11P25MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 2 - register "usb2_ports[1]" = "{ - .enable = 1, - .ocpin = OC1, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 1 - register "usb2_ports[2]" = "{ - .enable = 1, - .ocpin = OC3, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 3 - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port - register "usb2_ports[4]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 4 - register "usb2_ports[5]" = "{ - .enable = 1, - .ocpin = OC0, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A port 0 - register "usb2_ports[9]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # BT - - register "usb3_ports[0]" = "{ - .enable = 1, - .ocpin = OC2, - .tx_de_emp = 0x00, - .tx_downscale_amp = 0x00, - .gen2_tx_rate0_uniq_tran_enable = 0, - .gen2_tx_rate0_uniq_tran = 0x00, - .gen2_tx_rate1_uniq_tran_enable = 0, - .gen2_tx_rate1_uniq_tran = 0x00, - .gen2_tx_rate2_uniq_tran_enable = 1, - .gen2_tx_rate2_uniq_tran = 0x4c, - .gen2_tx_rate3_uniq_tran_enable = 0, - .gen2_tx_rate3_uniq_tran = 0x00, - .gen2_rx_tuning_enable = 0x0f, - .gen2_rx_tuning_params = 0x45, - .gen2_rx_filter_sel = 0x44, - }" # Type-A Port 2 - register "usb3_ports[1]" = "USB3_PORT_GEN2_DEFAULT(OC3)" # Type-A Port 3 - register "usb3_ports[2]" = "{ - .enable = 1, - .ocpin = OC1, - .tx_de_emp = 0x00, - .tx_downscale_amp = 0x00, - .gen2_tx_rate0_uniq_tran_enable = 0, - .gen2_tx_rate0_uniq_tran = 0x00, - .gen2_tx_rate1_uniq_tran_enable = 0, - .gen2_tx_rate1_uniq_tran = 0x00, - .gen2_tx_rate2_uniq_tran_enable = 1, - .gen2_tx_rate2_uniq_tran = 0x4c, - .gen2_tx_rate3_uniq_tran_enable = 0, - .gen2_tx_rate3_uniq_tran = 0x00, - .gen2_rx_tuning_enable = 0x0f, - .gen2_rx_tuning_params = 0x3d, - .gen2_rx_filter_sel = 0x44, - }" # Type-A Port 1 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[4]" = "{ - .enable = 1, - .ocpin = OC0, - .tx_de_emp = 0x00, - .tx_downscale_amp = 0x00, - .gen2_tx_rate0_uniq_tran_enable = 0, - .gen2_tx_rate0_uniq_tran = 0x00, - .gen2_tx_rate1_uniq_tran_enable = 0, - .gen2_tx_rate1_uniq_tran = 0x00, - .gen2_tx_rate2_uniq_tran_enable = 1, - .gen2_tx_rate2_uniq_tran = 0x4c, - .gen2_tx_rate3_uniq_tran_enable = 0, - .gen2_tx_rate3_uniq_tran = 0x00, - .gen2_rx_tuning_enable = 0x0f, - .gen2_rx_tuning_params = 0x45, - .gen2_rx_filter_sel = 0x44, - }" # Type-A Port 0 - register "usb3_ports[5]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_de_emp = 0x00, - .tx_downscale_amp = 0x00, - .gen2_tx_rate0_uniq_tran_enable = 0, - .gen2_tx_rate0_uniq_tran = 0x00, - .gen2_tx_rate1_uniq_tran_enable = 0, - .gen2_tx_rate1_uniq_tran = 0x00, - .gen2_tx_rate2_uniq_tran_enable = 1, - .gen2_tx_rate2_uniq_tran = 0x4c, - .gen2_tx_rate3_uniq_tran_enable = 0, - .gen2_tx_rate3_uniq_tran = 0x00, - .gen2_rx_tuning_enable = 0x0f, - .gen2_rx_tuning_params = 0x45, - .gen2_rx_filter_sel = 0x44, - }" # Type-A Port 4 - - # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ - USB_PORT_WAKE_ENABLE(6)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ - USB_PORT_WAKE_ENABLE(6)" - - # Enable eMMC HS400 - register "ScsEmmcHs400Enabled" = "1" - - # EMMC Tx CMD Delay - # Refer to EDS-Vol2-14.3.7. - # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" - - # EMMC TX DATA Delay 1 - # Refer to EDS-Vol2-14.3.8. - # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. - # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" - - # EMMC TX DATA Delay 2 - # Refer to EDS-Vol2-14.3.9. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. - # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" - - # EMMC RX CMD/DATA Delay 1 - # Refer to EDS-Vol2-14.3.10. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. - # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" - - # EMMC RX CMD/DATA Delay 2 - # Refer to EDS-Vol2-14.3.12. - # [17:16] stands for Rx Clock before Output Buffer, - # 00: Rx clock after output buffer, - # 01: Rx clock before output buffer, - # 10: Automatic selection based on working mode. - # 11: Reserved - # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" - - # EMMC Rx Strobe Delay - # Refer to EDS-Vol2-14.3.11. - # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. - # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" - - # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. - register "PchHdaAudioLinkSsp1" = "0" - register "PchHdaAudioLinkDmic0" = "0" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| I2C0 | RFU | - #| I2C2 | PS175 | - #| I2C3 | MST | - #| I2C4 | Audio | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 0, - .fall_time_ns = 0, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - .i2c[4] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - }" - - # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" - # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" - # Uses CLK SRC 0 - register "PcieClkSrcUsage[0]" = "6" - register "PcieClkSrcClkReq[0]" = "0" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "vSD3_CD_B" - - # SATA port 1 Gen3 Strength - # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB - register "sata_port[1].TxGen3DeEmphEnable" = "1" - register "sata_port[1].TxGen3DeEmph" = "0x20" - - device domain 0 on - device pci 04.0 on - chip drivers/intel/dptf - ## Active Policy - register "policies.active[0]" = "{.target=DPTF_CPU, - .thresholds={TEMP_PCT(94, 0),}}" - register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, - .thresholds={TEMP_PCT(65, 90), - TEMP_PCT(61, 80), - TEMP_PCT(57, 70), - TEMP_PCT(53, 60), - TEMP_PCT(49, 50), - TEMP_PCT(45, 40), - TEMP_PCT(41, 0),}}" - - ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 68, 5000)" - - ## Critical Policy - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)" - - ## Power Limits Control - # PL1 is fixed at 15W, avg over 28-32s interval - # 15-51W PL2 in 1000mW increments, avg over 28-32s interval - register "controls.power_limits.pl1" = "{ - .min_power = 15000, - .max_power = 15000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200,}" - register "controls.power_limits.pl2" = "{ - .min_power = 15000, - .max_power = 51000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 1000,}" - - ## Charger Performance Control (Control, mA) - register "controls.charger_perf[0]" = "{ 255, 1700 }" - register "controls.charger_perf[1]" = "{ 24, 1500 }" - register "controls.charger_perf[2]" = "{ 16, 1000 }" - register "controls.charger_perf[3]" = "{ 8, 500 }" - - ## Fan Performance Control (Percent, Speed, Noise, Power) - register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" - register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" - register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" - register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" - register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" - register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" - register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" - register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" - register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" - register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" - - # Fan options - register "options.fan.fine_grained_control" = "1" - register "options.fan.step_size" = "2" - - device generic 0 on end - end - end # DPTF 0x1903 - device pci 14.0 on - chip drivers/usb/acpi - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Left"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 3)" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Right"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Right"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 2.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Middle"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Left"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 2.5 on end - end - chip drivers/usb/acpi - device usb 2.6 off end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Left"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Right"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Right"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 3)" - device usb 3.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Left"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 3.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Middle"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 3.5 on end - end - end - end - end # USB xHCI - device pci 15.0 off - # RFU - Reserved for Future Use. - end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 on - chip drivers/i2c/generic - register "hid" = ""1AF80175"" - register "name" = ""PS17"" - register "desc" = ""Parade PS175"" - device i2c 4a on end - end - end # I2C #2, PCON PS175. - device pci 15.3 on - chip drivers/i2c/generic - register "hid" = ""10EC2142"" - register "name" = ""RTD2"" - register "desc" = ""Realtek RTD2142"" - device i2c 4a on end - end - end # I2C #3, Realtek RTD2142. - device pci 16.0 on end # Management Engine Interface 1 - device pci 19.0 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" - register "property_count" = "1" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on end - end - end #I2C #4 - device pci 1a.0 on end # eMMC - device pci 1c.6 on - chip drivers/net - register "customized_leds" = "0x05af" - register "wake" = "GPE0_DW1_07" # GPP_C7 - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" - register "stop_delay_ms" = "12" # NIC needs time to quiesce - register "stop_off_delay_ms" = "1" - register "has_power_resource" = "1" - register "device_index" = "0" - device pci 00.0 on end - end - register "PcieRpSlotImplemented[6]" = "1" - end # RTL8111H Ethernet NIC - device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) - register "PcieRpSlotImplemented[10]" = "1" - end - device pci 1e.3 off end # GSPI #1 - end - - # VR Settings Configuration for 4 Domains - #+----------------+-------+-------+-------+-------+ - #| Domain/Setting | SA | IA | GTUS | GTS | - #+----------------+-------+-------+-------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | - #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | - #+----------------+-------+-------+-------+-------+ - #Note: IccMax settings are moved to SoC code - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 1004, - .dc_loadline = 1004, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 181, - .dc_loadline = 181, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 319, - .dc_loadline = 319, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 319, - .dc_loadline = 319, - }" - -end diff --git a/src/mainboard/google/hatch/variants/faffy/Makefile.inc b/src/mainboard/google/hatch/variants/faffy/Makefile.inc deleted file mode 100644 index 3b5b7d000d..0000000000 --- a/src/mainboard/google/hatch/variants/faffy/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ramstage-y += gpio.c -bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/faffy/data.vbt b/src/mainboard/google/hatch/variants/faffy/data.vbt Binary files differdeleted file mode 100644 index cda1c25d7d..0000000000 --- a/src/mainboard/google/hatch/variants/faffy/data.vbt +++ /dev/null diff --git a/src/mainboard/google/hatch/variants/faffy/gpio.c b/src/mainboard/google/hatch/variants/faffy/gpio.c deleted file mode 100644 index 996edc4fc7..0000000000 --- a/src/mainboard/google/hatch/variants/faffy/gpio.c +++ /dev/null @@ -1,117 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <commonlib/helpers.h> - -static const struct pad_config gpio_table[] = { - /* A16 : SD_OC_ODL */ - PAD_CFG_GPI(GPP_A16, NONE, DEEP), - /* A18 : LAN_PE_ISOLATE_ODL */ - PAD_CFG_GPO(GPP_A18, 1, DEEP), - /* A23 : M2_WLAN_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), - - /* B5 : LAN_CLKREQ_ODL */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), - - /* C0 : SMBCLK */ - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), - /* C1 : SMBDATA */ - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - /* C6: M2_WLAN_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), - /* C7 : LAN_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), - /* C10 : PCH_PCON_RST_ODL */ - PAD_CFG_GPO(GPP_C10, 1, DEEP), - /* C11 : PCH_PCON_PDB_ODL */ - PAD_CFG_GPO(GPP_C11, 1, DEEP), - /* C15 : WLAN_OFF_L */ - PAD_CFG_GPO(GPP_C15, 1, DEEP), - - /* E2 : EN_PP_MST_OD */ - PAD_CFG_GPO(GPP_E2, 1, DEEP), - /* E9 : USB_A0_OC_ODL */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - /* E10 : USB_A1_OC_ODL */ - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), - - /* F11 : EMMC_CMD */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), - /* F12 : EMMC_DATA0 */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), - /* F13 : EMMC_DATA1 */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), - /* F14 : EMMC_DATA2 */ - PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), - /* F15 : EMMC_DATA3 */ - PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), - /* F16 : EMMC_DATA4 */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), - /* F17 : EMMC_DATA5 */ - PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), - /* F18 : EMMC_DATA6 */ - PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), - /* F19 : EMMC_DATA7 */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - /* F20 : EMMC_RCLK */ - PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), - /* F21 : EMMC_CLK */ - PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), - /* F22 : EMMC_RST_L */ - PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), - - /* H4: PCH_I2C_PCON_SDA */ - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* H5: PCH_I2C_PCON_SCL */ - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* H22 : PWM_PP3300_BIOZZER */ - PAD_CFG_GPO(GPP_H22, 0, DEEP), -}; - -const struct pad_config *override_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* B14 : GPP_B14_STRAP */ - PAD_NC(GPP_B14, NONE), - /* B22 : GPP_B22_STRAP */ - PAD_NC(GPP_B22, NONE), - /* E19 : GPP_E19_STRAP */ - PAD_NC(GPP_E19, NONE), - /* E21 : GPP_E21_STRAP */ - PAD_NC(GPP_E21, NONE), - /* B15 : H1_SLAVE_SPI_CS_L */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* B16 : H1_SLAVE_SPI_CLK */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* B17 : H1_SLAVE_SPI_MISO_R */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* B18 : H1_SLAVE_SPI_MOSI_R */ - PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* C14 : BT_DISABLE_L */ - PAD_CFG_GPO(GPP_C14, 0, DEEP), - /* PCH_WP_OD */ - PAD_CFG_GPI(GPP_C20, NONE, DEEP), - /* C21 : H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), - /* C22 : EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_C22, NONE, DEEP), - /* C23 : WLAN_PE_RST# */ - PAD_CFG_GPO(GPP_C23, 1, DEEP), - /* E1 : M2_SSD_PEDET */ - PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), - /* E5 : SATA_DEVSLP1 */ - PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), -}; - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} diff --git a/src/mainboard/google/hatch/variants/faffy/include/variant/ec.h b/src/mainboard/google/hatch/variants/faffy/include/variant/ec.h deleted file mode 100644 index 59fb3783c5..0000000000 --- a/src/mainboard/google/hatch/variants/faffy/include/variant/ec.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_EC_H -#define VARIANT_EC_H - -#include <puff/ec.h> - -#endif diff --git a/src/mainboard/google/hatch/variants/faffy/include/variant/gpio.h b/src/mainboard/google/hatch/variants/faffy/include/variant/gpio.h deleted file mode 100644 index 79a141008f..0000000000 --- a/src/mainboard/google/hatch/variants/faffy/include/variant/gpio.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include <baseboard/gpio.h> - -#endif diff --git a/src/mainboard/google/hatch/variants/faffy/overridetree.cb b/src/mainboard/google/hatch/variants/faffy/overridetree.cb deleted file mode 100644 index 1ac9414c6a..0000000000 --- a/src/mainboard/google/hatch/variants/faffy/overridetree.cb +++ /dev/null @@ -1,521 +0,0 @@ -chip soc/intel/cannonlake - register "tcc_offset" = "5" # TCC of 95C - - register "power_limits_config" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 51, - }" - - # Auto-switch between X4 NVMe and X2 NVMe. - register "TetonGlacierMode" = "1" - - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - [PchSerialIoIndexSPI0] = PchSerialIoPci, - [PchSerialIoIndexSPI1] = PchSerialIoPci, - [PchSerialIoIndexSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoSkipInit, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - - # USB configuration - register "usb2_ports[0]" = "{ - .enable = 1, - .ocpin = OC2, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_11P25MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 2 - register "usb2_ports[1]" = "{ - .enable = 1, - .ocpin = OC1, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 1 - register "usb2_ports[2]" = "{ - .enable = 1, - .ocpin = OC3, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 3 - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port - register "usb2_ports[4]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 4 - register "usb2_ports[5]" = "{ - .enable = 1, - .ocpin = OC0, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A port 0 - register "usb2_ports[6]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # PL2303 - register "usb2_ports[9]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # BT - - register "usb3_ports[0]" = "{ - .enable = 1, - .ocpin = OC2, - .tx_de_emp = 0x00, - .tx_downscale_amp = 0x00, - .gen2_tx_rate0_uniq_tran_enable = 0, - .gen2_tx_rate0_uniq_tran = 0x00, - .gen2_tx_rate1_uniq_tran_enable = 0, - .gen2_tx_rate1_uniq_tran = 0x00, - .gen2_tx_rate2_uniq_tran_enable = 1, - .gen2_tx_rate2_uniq_tran = 0x4c, - .gen2_tx_rate3_uniq_tran_enable = 0, - .gen2_tx_rate3_uniq_tran = 0x00, - .gen2_rx_tuning_enable = 0x0f, - .gen2_rx_tuning_params = 0x45, - .gen2_rx_filter_sel = 0x44, - }" # Type-A Port 2 - register "usb3_ports[1]" = "USB3_PORT_GEN2_DEFAULT(OC3)" # Type-A Port 3 - register "usb3_ports[2]" = "{ - .enable = 1, - .ocpin = OC1, - .tx_de_emp = 0x00, - .tx_downscale_amp = 0x00, - .gen2_tx_rate0_uniq_tran_enable = 0, - .gen2_tx_rate0_uniq_tran = 0x00, - .gen2_tx_rate1_uniq_tran_enable = 0, - .gen2_tx_rate1_uniq_tran = 0x00, - .gen2_tx_rate2_uniq_tran_enable = 1, - .gen2_tx_rate2_uniq_tran = 0x4c, - .gen2_tx_rate3_uniq_tran_enable = 0, - .gen2_tx_rate3_uniq_tran = 0x00, - .gen2_rx_tuning_enable = 0x0f, - .gen2_rx_tuning_params = 0x3d, - .gen2_rx_filter_sel = 0x44, - }" # Type-A Port 1 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[4]" = "{ - .enable = 1, - .ocpin = OC0, - .tx_de_emp = 0x00, - .tx_downscale_amp = 0x00, - .gen2_tx_rate0_uniq_tran_enable = 0, - .gen2_tx_rate0_uniq_tran = 0x00, - .gen2_tx_rate1_uniq_tran_enable = 0, - .gen2_tx_rate1_uniq_tran = 0x00, - .gen2_tx_rate2_uniq_tran_enable = 1, - .gen2_tx_rate2_uniq_tran = 0x4c, - .gen2_tx_rate3_uniq_tran_enable = 0, - .gen2_tx_rate3_uniq_tran = 0x00, - .gen2_rx_tuning_enable = 0x0f, - .gen2_rx_tuning_params = 0x45, - .gen2_rx_filter_sel = 0x44, - }" # Type-A Port 0 - register "usb3_ports[5]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_de_emp = 0x00, - .tx_downscale_amp = 0x00, - .gen2_tx_rate0_uniq_tran_enable = 0, - .gen2_tx_rate0_uniq_tran = 0x00, - .gen2_tx_rate1_uniq_tran_enable = 0, - .gen2_tx_rate1_uniq_tran = 0x00, - .gen2_tx_rate2_uniq_tran_enable = 1, - .gen2_tx_rate2_uniq_tran = 0x4c, - .gen2_tx_rate3_uniq_tran_enable = 0, - .gen2_tx_rate3_uniq_tran = 0x00, - .gen2_rx_tuning_enable = 0x0f, - .gen2_rx_tuning_params = 0x45, - .gen2_rx_filter_sel = 0x44, - }" # Type-A Port 4 - - # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ - USB_PORT_WAKE_ENABLE(6)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ - USB_PORT_WAKE_ENABLE(6)" - - # Enable eMMC HS400 - register "ScsEmmcHs400Enabled" = "1" - - # EMMC Tx CMD Delay - # Refer to EDS-Vol2-14.3.7. - # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" - - # EMMC TX DATA Delay 1 - # Refer to EDS-Vol2-14.3.8. - # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. - # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" - - # EMMC TX DATA Delay 2 - # Refer to EDS-Vol2-14.3.9. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. - # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" - - # EMMC RX CMD/DATA Delay 1 - # Refer to EDS-Vol2-14.3.10. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. - # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" - - # EMMC RX CMD/DATA Delay 2 - # Refer to EDS-Vol2-14.3.12. - # [17:16] stands for Rx Clock before Output Buffer, - # 00: Rx clock after output buffer, - # 01: Rx clock before output buffer, - # 10: Automatic selection based on working mode. - # 11: Reserved - # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" - - # EMMC Rx Strobe Delay - # Refer to EDS-Vol2-14.3.11. - # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. - # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" - - # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. - register "PchHdaAudioLinkSsp1" = "0" - register "PchHdaAudioLinkDmic0" = "0" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| I2C0 | RFU | - #| I2C2 | PS175 | - #| I2C3 | MST | - #| I2C4 | Audio | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 0, - .fall_time_ns = 0, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - .i2c[4] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - }" - - # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" - # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" - # Uses CLK SRC 0 - register "PcieClkSrcUsage[0]" = "6" - register "PcieClkSrcClkReq[0]" = "0" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "vSD3_CD_B" - - # SATA port 1 Gen3 Strength - # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB - register "sata_port[1].TxGen3DeEmphEnable" = "1" - register "sata_port[1].TxGen3DeEmph" = "0x20" - - device domain 0 on - device pci 04.0 on - chip drivers/intel/dptf - ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 73, 60000)" - - ## Critical Policy - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)" - - ## Power Limits Control - # 10-15W PL1 in 200mW increments, avg over 28-32s interval - # 15-51W PL2 in 1000mW increments, avg over 28-32s interval - register "controls.power_limits.pl1" = "{ - .min_power = 10000, - .max_power = 15000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200,}" - register "controls.power_limits.pl2" = "{ - .min_power = 15000, - .max_power = 51000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 1000,}" - - device generic 0 on end - end - end # DPTF 0x1903 - device pci 14.0 on - chip drivers/usb/acpi - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Left"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 3)" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Right"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Right"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 2.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Middle"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Left"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 2.5 on end - end - chip drivers/usb/acpi - device usb 2.6 off end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Left"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Right"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Right"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 3)" - device usb 3.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Left"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 3.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Middle"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 3.5 on end - end - end - end - end # USB xHCI - device pci 15.0 off - # RFU - Reserved for Future Use. - end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 on - chip drivers/i2c/generic - register "hid" = ""1AF80175"" - register "name" = ""PS17"" - register "desc" = ""Parade PS175"" - device i2c 4a on end - end - end # I2C #2, PCON PS175. - device pci 15.3 on - chip drivers/i2c/generic - register "hid" = ""10EC2142"" - register "name" = ""RTD2"" - register "desc" = ""Realtek RTD2142"" - device i2c 4a on end - end - end # I2C #3, Realtek RTD2142. - device pci 16.0 on end # Management Engine Interface 1 - device pci 19.0 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" - register "property_count" = "1" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on end - end - end #I2C #4 - device pci 1a.0 on end # eMMC - device pci 1c.6 on - chip drivers/net - register "customized_leds" = "0x05af" - register "wake" = "GPE0_DW1_07" # GPP_C7 - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" - register "stop_delay_ms" = "12" # NIC needs time to quiesce - register "stop_off_delay_ms" = "1" - register "has_power_resource" = "1" - register "device_index" = "0" - device pci 00.0 on end - end - register "PcieRpSlotImplemented[6]" = "1" - end # RTL8111H Ethernet NIC - device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) - register "PcieRpSlotImplemented[10]" = "1" - end - device pci 1e.3 off end # GSPI #1 - end - - # VR Settings Configuration for 4 Domains - #+----------------+-------+-------+-------+-------+ - #| Domain/Setting | SA | IA | GTUS | GTS | - #+----------------+-------+-------+-------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | - #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | - #+----------------+-------+-------+-------+-------+ - #Note: IccMax settings are moved to SoC code - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 1004, - .dc_loadline = 1004, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 181, - .dc_loadline = 181, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 319, - .dc_loadline = 319, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 319, - .dc_loadline = 319, - }" - -end diff --git a/src/mainboard/google/hatch/variants/genesis/Makefile.inc b/src/mainboard/google/hatch/variants/genesis/Makefile.inc deleted file mode 100644 index 3b5b7d000d..0000000000 --- a/src/mainboard/google/hatch/variants/genesis/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ramstage-y += gpio.c -bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/genesis/gpio.c b/src/mainboard/google/hatch/variants/genesis/gpio.c deleted file mode 100644 index 66a1b8aec1..0000000000 --- a/src/mainboard/google/hatch/variants/genesis/gpio.c +++ /dev/null @@ -1,145 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <commonlib/helpers.h> - -static const struct pad_config gpio_table[] = { - /* A16 : SD_OC_ODL */ - PAD_CFG_GPI(GPP_A16, NONE, DEEP), - /* A18 : LAN_PE_ISOLATE_ODL */ - PAD_CFG_GPO(GPP_A18, 1, DEEP), - /* A19 : PCH_PCON0_PDB_ODL */ - PAD_CFG_GPO(GPP_A19, 1, DEEP), - /* A20 : LAN_I350_WAKE# */ - PAD_CFG_GPI_IRQ_WAKE(GPP_A20, NONE, DEEP, LEVEL, INVERT), - /* A23 : M2_WLAN_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), - - /* B5 : LAN_CLKREQ_ODL */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), - /* B6 : M2_SSD_CLKREQ_ODL */ - PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), - /* B7 : M2_TPU0_CLKREQ_ODL */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), - /* B8 : CLK_PCIE_REQ3 (not connected) */ - PAD_NC(GPP_B8, NONE), - /* B9 : M2_TPU1_CLKREQ_ODL */ - PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), - /* B10 : M2_WLAN_CLKREQ_ODL */ - PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), - - /* C0 : SMBCLK */ - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), - /* C1 : SMBDATA */ - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - /* C3 : PCH_MBCLK1_R (i350) */ - PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), - /* C4 : PCH_MBDAT1_R (i350) */ - PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), - /* C6: M2_WLAN_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), - /* C7 : LAN_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), - /* C10 : PCH_PCON_RST_ODL */ - PAD_CFG_GPO(GPP_C10, 1, DEEP), - /* C11 : PCH_PCON1_PDB_ODL */ - PAD_CFG_GPO(GPP_C11, 1, DEEP), - /* C15 : WLAN_OFF_L */ - PAD_CFG_GPO(GPP_C15, 1, DEEP), - - /* E2 : Not connected */ - PAD_NC(GPP_E2, NONE), - /* E3 : TPU_RST_PIN40 */ - PAD_CFG_GPO(GPP_E3, 1, DEEP), - /* E7 : TPU_RST_PIN42 */ - PAD_CFG_GPO(GPP_E7, 1, DEEP), - /* E9 : PU 10K to PP3300_SOC_A */ - PAD_NC(GPP_E9, NONE), - /* E10 : USB_A1_OC_ODL */ - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), - /* E15 : PCH_TYPEC_UPFB */ - PAD_CFG_GPI(GPP_E15, NONE, DEEP), - - /* F11 : EMMC_CMD */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), - /* F12 : EMMC_DATA0 */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), - /* F13 : EMMC_DATA1 */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), - /* F14 : EMMC_DATA2 */ - PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), - /* F15 : EMMC_DATA3 */ - PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), - /* F16 : EMMC_DATA4 */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), - /* F17 : EMMC_DATA5 */ - PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), - /* F18 : EMMC_DATA6 */ - PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), - /* F19 : EMMC_DATA7 */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - /* F20 : EMMC_RCLK */ - PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), - /* F21 : EMMC_CLK */ - PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), - /* F22 : EMMC_RST_L */ - PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), - - /* H4: PCH_I2C_PCON_SDA */ - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* H5: PCH_I2C_PCON_SCL */ - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* H6 : PCH_I2C_TPU_SDA */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), - /* H7 : PCH_I2C_TPU_SCL */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), - /* H22 : PWM_PP3300_BIOZZER */ - PAD_CFG_GPO(GPP_H22, 0, DEEP), -}; - -const struct pad_config *override_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* B14 : GPP_B14_STRAP */ - PAD_NC(GPP_B14, NONE), - /* B22 : GPP_B22_STRAP */ - PAD_NC(GPP_B22, NONE), - /* E19 : GPP_E19_STRAP */ - PAD_NC(GPP_E19, NONE), - /* E21 : GPP_E21_STRAP */ - PAD_NC(GPP_E21, NONE), - /* B15 : H1_SLAVE_SPI_CS_L */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* B16 : H1_SLAVE_SPI_CLK */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* B17 : H1_SLAVE_SPI_MISO_R */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* B18 : H1_SLAVE_SPI_MOSI_R */ - PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* C14 : BT_DISABLE_L */ - PAD_CFG_GPO(GPP_C14, 0, DEEP), - /* PCH_WP_OD */ - PAD_CFG_GPI(GPP_C20, NONE, DEEP), - /* C21 : H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), - /* C22 : EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_C22, NONE, DEEP), - /* C23 : WLAN_PE_RST# */ - PAD_CFG_GPO(GPP_C23, 1, DEEP), - /* E1 : M2_SSD_PEDET */ - PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), - /* E5 : SATA_DEVSLP1 */ - PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), -}; - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} diff --git a/src/mainboard/google/hatch/variants/genesis/include/variant/ec.h b/src/mainboard/google/hatch/variants/genesis/include/variant/ec.h deleted file mode 100644 index 59fb3783c5..0000000000 --- a/src/mainboard/google/hatch/variants/genesis/include/variant/ec.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_EC_H -#define VARIANT_EC_H - -#include <puff/ec.h> - -#endif diff --git a/src/mainboard/google/hatch/variants/genesis/include/variant/gpio.h b/src/mainboard/google/hatch/variants/genesis/include/variant/gpio.h deleted file mode 100644 index 79a141008f..0000000000 --- a/src/mainboard/google/hatch/variants/genesis/include/variant/gpio.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include <baseboard/gpio.h> - -#endif diff --git a/src/mainboard/google/hatch/variants/genesis/overridetree.cb b/src/mainboard/google/hatch/variants/genesis/overridetree.cb deleted file mode 100644 index b42ca911bc..0000000000 --- a/src/mainboard/google/hatch/variants/genesis/overridetree.cb +++ /dev/null @@ -1,531 +0,0 @@ -chip soc/intel/cannonlake - # Auto-switch between X4 NVMe and X2 NVMe. - register "TetonGlacierMode" = "1" - - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - [PchSerialIoIndexSPI0] = PchSerialIoPci, - [PchSerialIoIndexSPI1] = PchSerialIoPci, - [PchSerialIoIndexSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoSkipInit, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - - # USB configuration - register "usb2_ports[0]" = "{ - .enable = 1, - .ocpin = OC2, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_11P25MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 2 - register "usb2_ports[1]" = "{ - .enable = 1, - .ocpin = OC1, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 1 - register "usb2_ports[2]" = "{ - .enable = 1, - .ocpin = OC3, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 3 - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port - register "usb2_ports[4]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 4 - register "usb2_ports[5]" = "{ - .enable = 1, - .ocpin = OC0, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A port 0 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" - register "usb2_ports[9]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # BT - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 - - # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ - USB_PORT_WAKE_ENABLE(6)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ - USB_PORT_WAKE_ENABLE(6)" - - # Enable eMMC HS400 - register "ScsEmmcHs400Enabled" = "1" - - # EMMC Tx CMD Delay - # Refer to EDS-Vol2-14.3.7. - # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" - - # EMMC TX DATA Delay 1 - # Refer to EDS-Vol2-14.3.8. - # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. - # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" - - # EMMC TX DATA Delay 2 - # Refer to EDS-Vol2-14.3.9. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. - # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" - - # EMMC RX CMD/DATA Delay 1 - # Refer to EDS-Vol2-14.3.10. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. - # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" - - # EMMC RX CMD/DATA Delay 2 - # Refer to EDS-Vol2-14.3.12. - # [17:16] stands for Rx Clock before Output Buffer, - # 00: Rx clock after output buffer, - # 01: Rx clock before output buffer, - # 10: Automatic selection based on working mode. - # 11: Reserved - # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" - - # EMMC Rx Strobe Delay - # Refer to EDS-Vol2-14.3.11. - # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. - # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" - - # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. - register "PchHdaAudioLinkSsp1" = "0" - register "PchHdaAudioLinkDmic0" = "0" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| I2C0 | RFU | - #| I2C2 | PS175 | - #| I2C3 | MST | - #| I2C4 | Audio | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 0, - .fall_time_ns = 0, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - .i2c[4] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - }" - - # PCIe root port 7 for LAN - register "PcieRpEnable[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" - # Uses CLK SRC 0 - register "PcieClkSrcUsage[0]" = "6" - register "PcieClkSrcClkReq[0]" = "0" - - # PCIe root port 8 for WLAN - register "PcieRpEnable[7]" = "1" - register "PcieRpLtrEnable[7]" = "1" - # Uses CLK SRC 5 - register "PcieClkSrcUsage[5]" = "7" - register "PcieClkSrcClkReq[5]" = "5" - - # PCIe root port 9 for SSD (PCIe Lanes 11, 12) - register "PcieRpEnable[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" - # RP 9 uses CLK SRC 1 - register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcClkReq[1]" = "1" - - # PCIe root port 10 disabled - register "PcieRpEnable[9]" = "0" - - # PCIe root port 11 TPU1 - register "PcieRpEnable[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" - # RP 11 uses CLK SRC 1 - register "PcieClkSrcUsage[4]" = "10" - register "PcieClkSrcClkReq[4]" = "4" - - # PCIe root port 12 TPU0 - register "PcieRpEnable[11]" = "1" - register "PcieRpLtrEnable[11]" = "1" - # RP 11 uses CLK SRC 1 - register "PcieClkSrcUsage[2]" = "11" - register "PcieClkSrcClkReq[2]" = "2" - - # PCIe port 13 for i350 NIC (x4) - register "PcieRpEnable[12]" = "1" - register "PcieRpLtrEnable[12]" = "1" - # RP 13 uses CLK SRC 3 - register "PcieClkSrcUsage[3]" = "12" - # RP 13 does not use a source clock request line - # NOTE: Any value other than a valid source-clock-request (0-5) is - # effectively "not connected" - register "PcieClkSrcClkReq[3]" = "0xFF" - # Disable the remaining ports 14-16 - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "vSD3_CD_B" - - # SATA port 1 Gen3 Strength - # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB - register "sata_port[1].TxGen3DeEmphEnable" = "1" - register "sata_port[1].TxGen3DeEmph" = "0x20" - - device domain 0 on - device pci 04.0 on - chip drivers/intel/dptf - ## Active Policy - register "policies.active[0]" = "{.target=DPTF_CPU, - .thresholds={TEMP_PCT(94, 0),}}" - register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, - .thresholds={TEMP_PCT(72, 90), - TEMP_PCT(68, 80), - TEMP_PCT(62, 70), - TEMP_PCT(54, 60), - TEMP_PCT(46, 50), - TEMP_PCT(39, 40),}}" - - ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000)" - - ## Critical Policy - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)" - - ## Power Limits Control - # PL1 is fixed at 15W, avg over 28-32s interval - # 51-51W PL2 in 1000mW increments, avg over 28-32s interval - register "controls.power_limits.pl1" = "{ - .min_power = 15000, - .max_power = 15000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 125,}" - register "controls.power_limits.pl2" = "{ - .min_power = 51000, - .max_power = 51000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 1000,}" - - ## Charger Performance Control (Control, mA) - register "controls.charger_perf[0]" = "{ 255, 1700 }" - register "controls.charger_perf[1]" = "{ 24, 1500 }" - register "controls.charger_perf[2]" = "{ 16, 1000 }" - register "controls.charger_perf[3]" = "{ 8, 500 }" - - ## Fan Performance Control (Percent, Speed, Noise, Power) - register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" - register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" - register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" - register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" - register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" - register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" - register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" - register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" - register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" - register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" - - # Fan options - register "options.fan.fine_grained_control" = "1" - register "options.fan.step_size" = "2" - - device generic 0 on end - end - end # DPTF 0x1903 - device pci 14.0 on - chip drivers/usb/acpi - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Left"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 3)" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Right"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Right"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 2.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Middle"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Left"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 2.5 on end - end - chip drivers/usb/acpi - device usb 2.6 off end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Left"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Right"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Right"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 3)" - device usb 3.3 on end - end - chip drivers/usb/acpi - # USB3 Port 5 is not populated - device usb 3.4 off end - end - chip drivers/usb/acpi - register "desc" = ""USB3 M.2 HDMI-to-USB"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(2, 0)" - device usb 3.5 on end - end - end - end - end # USB xHCI - device pci 15.0 off - # RFU - Reserved for Future Use. - end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 on - chip drivers/i2c/generic - register "hid" = ""1AF80175"" - register "name" = ""PS17"" - register "desc" = ""Parade PS175"" - device i2c 4a on end - end - end # I2C #2, PCON PS175. - device pci 15.3 on - chip drivers/i2c/generic - register "hid" = ""10EC2142"" - register "name" = ""RTD2"" - register "desc" = ""Realtek RTD2142"" - device i2c 4a on end - end - end # I2C #3, Realtek RTD2142. - device pci 16.0 on end # Management Engine Interface 1 - device pci 19.0 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" - register "property_count" = "1" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on end - end - end #I2C #4 - device pci 1a.0 off end # eMMC - device pci 1c.6 on # PCI Root Port 7 (LAN) - chip drivers/net # RTL8111H Ethernet NIC - register "customized_leds" = "0x05af" - register "wake" = "GPE0_DW1_07" # GPP_C7 - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" - register "stop_delay_ms" = "12" # NIC needs time to quiesce - register "stop_off_delay_ms" = "1" - register "has_power_resource" = "1" - register "device_index" = "0" - device pci 00.0 on end - end - end - device pci 1c.7 on # PCI Root Port 8 (WLAN) - register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot - end - device pci 1d.0 on # PCI Root Port 9 (TPU) - register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot - end - device pci 1d.1 off end # PCI Root Port 10 (Not connected) - device pci 1d.2 on end # PCI Root Port 11 (TPU1) - register "PcieRpSlotImplemented[10]" = "1" # M.2 Slot - device pci 1d.3 on end # PCI Root Port 12 (TPU0) - register "PcieRpSlotImplemented[11]" = "1" # M.2 Slot - device pci 1d.4 on # PCI Root Port 13 (X4 i350 NIC) - register "PcieRpSlotImplemented[12]" = "0" # Built-in - end - device pci 1d.5 on end # PCI Root Port 14 (non-root) - device pci 1d.6 on end # PCI Root Port 15 (non-root) - device pci 1d.7 on end # PCI Root Port 16 (non-root) - device pci 1e.3 off end # GSPI #1 - end - - # VR Settings Configuration for 4 Domains - #+----------------+-------+-------+-------+-------+ - #| Domain/Setting | SA | IA | GTUS | GTS | - #+----------------+-------+-------+-------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | - #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | - #+----------------+-------+-------+-------+-------+ - #Note: IccMax settings are moved to SoC code - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 1004, - .dc_loadline = 1004, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 181, - .dc_loadline = 181, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 319, - .dc_loadline = 319, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 319, - .dc_loadline = 319, - }" - -end diff --git a/src/mainboard/google/hatch/variants/kaisa/Makefile.inc b/src/mainboard/google/hatch/variants/kaisa/Makefile.inc deleted file mode 100644 index 3b5b7d000d..0000000000 --- a/src/mainboard/google/hatch/variants/kaisa/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ramstage-y += gpio.c -bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/kaisa/data.vbt b/src/mainboard/google/hatch/variants/kaisa/data.vbt Binary files differdeleted file mode 100644 index cda1c25d7d..0000000000 --- a/src/mainboard/google/hatch/variants/kaisa/data.vbt +++ /dev/null diff --git a/src/mainboard/google/hatch/variants/kaisa/gpio.c b/src/mainboard/google/hatch/variants/kaisa/gpio.c deleted file mode 100644 index 996edc4fc7..0000000000 --- a/src/mainboard/google/hatch/variants/kaisa/gpio.c +++ /dev/null @@ -1,117 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <commonlib/helpers.h> - -static const struct pad_config gpio_table[] = { - /* A16 : SD_OC_ODL */ - PAD_CFG_GPI(GPP_A16, NONE, DEEP), - /* A18 : LAN_PE_ISOLATE_ODL */ - PAD_CFG_GPO(GPP_A18, 1, DEEP), - /* A23 : M2_WLAN_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), - - /* B5 : LAN_CLKREQ_ODL */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), - - /* C0 : SMBCLK */ - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), - /* C1 : SMBDATA */ - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - /* C6: M2_WLAN_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), - /* C7 : LAN_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), - /* C10 : PCH_PCON_RST_ODL */ - PAD_CFG_GPO(GPP_C10, 1, DEEP), - /* C11 : PCH_PCON_PDB_ODL */ - PAD_CFG_GPO(GPP_C11, 1, DEEP), - /* C15 : WLAN_OFF_L */ - PAD_CFG_GPO(GPP_C15, 1, DEEP), - - /* E2 : EN_PP_MST_OD */ - PAD_CFG_GPO(GPP_E2, 1, DEEP), - /* E9 : USB_A0_OC_ODL */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - /* E10 : USB_A1_OC_ODL */ - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), - - /* F11 : EMMC_CMD */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), - /* F12 : EMMC_DATA0 */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), - /* F13 : EMMC_DATA1 */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), - /* F14 : EMMC_DATA2 */ - PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), - /* F15 : EMMC_DATA3 */ - PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), - /* F16 : EMMC_DATA4 */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), - /* F17 : EMMC_DATA5 */ - PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), - /* F18 : EMMC_DATA6 */ - PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), - /* F19 : EMMC_DATA7 */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - /* F20 : EMMC_RCLK */ - PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), - /* F21 : EMMC_CLK */ - PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), - /* F22 : EMMC_RST_L */ - PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), - - /* H4: PCH_I2C_PCON_SDA */ - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* H5: PCH_I2C_PCON_SCL */ - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* H22 : PWM_PP3300_BIOZZER */ - PAD_CFG_GPO(GPP_H22, 0, DEEP), -}; - -const struct pad_config *override_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* B14 : GPP_B14_STRAP */ - PAD_NC(GPP_B14, NONE), - /* B22 : GPP_B22_STRAP */ - PAD_NC(GPP_B22, NONE), - /* E19 : GPP_E19_STRAP */ - PAD_NC(GPP_E19, NONE), - /* E21 : GPP_E21_STRAP */ - PAD_NC(GPP_E21, NONE), - /* B15 : H1_SLAVE_SPI_CS_L */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* B16 : H1_SLAVE_SPI_CLK */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* B17 : H1_SLAVE_SPI_MISO_R */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* B18 : H1_SLAVE_SPI_MOSI_R */ - PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* C14 : BT_DISABLE_L */ - PAD_CFG_GPO(GPP_C14, 0, DEEP), - /* PCH_WP_OD */ - PAD_CFG_GPI(GPP_C20, NONE, DEEP), - /* C21 : H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), - /* C22 : EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_C22, NONE, DEEP), - /* C23 : WLAN_PE_RST# */ - PAD_CFG_GPO(GPP_C23, 1, DEEP), - /* E1 : M2_SSD_PEDET */ - PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), - /* E5 : SATA_DEVSLP1 */ - PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), -}; - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} diff --git a/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h b/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h deleted file mode 100644 index 59fb3783c5..0000000000 --- a/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_EC_H -#define VARIANT_EC_H - -#include <puff/ec.h> - -#endif diff --git a/src/mainboard/google/hatch/variants/kaisa/include/variant/gpio.h b/src/mainboard/google/hatch/variants/kaisa/include/variant/gpio.h deleted file mode 100644 index 79a141008f..0000000000 --- a/src/mainboard/google/hatch/variants/kaisa/include/variant/gpio.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include <baseboard/gpio.h> - -#endif diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb deleted file mode 100644 index 50c6d0b1b1..0000000000 --- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb +++ /dev/null @@ -1,547 +0,0 @@ -chip soc/intel/cannonlake - register "tcc_offset" = "5" # TCC of 95C - - register "power_limits_config" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 51, - }" - - # Auto-switch between X4 NVMe and X2 NVMe. - register "TetonGlacierMode" = "1" - - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - [PchSerialIoIndexSPI0] = PchSerialIoPci, - [PchSerialIoIndexSPI1] = PchSerialIoPci, - [PchSerialIoIndexSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoSkipInit, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - - # USB configuration - register "usb2_ports[0]" = "{ - .enable = 1, - .ocpin = OC2, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_11P25MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 2 - register "usb2_ports[1]" = "{ - .enable = 1, - .ocpin = OC1, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 1 - register "usb2_ports[2]" = "{ - .enable = 1, - .ocpin = OC3, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 3 - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port - register "usb2_ports[4]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 4 - register "usb2_ports[5]" = "{ - .enable = 1, - .ocpin = OC0, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A port 0 - register "usb2_ports[9]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # BT - - register "usb3_ports[0]" = "{ - .enable = 1, - .ocpin = OC2, - .tx_de_emp = 0x00, - .tx_downscale_amp = 0x00, - .gen2_tx_rate0_uniq_tran_enable = 0, - .gen2_tx_rate0_uniq_tran = 0x00, - .gen2_tx_rate1_uniq_tran_enable = 0, - .gen2_tx_rate1_uniq_tran = 0x00, - .gen2_tx_rate2_uniq_tran_enable = 1, - .gen2_tx_rate2_uniq_tran = 0x4c, - .gen2_tx_rate3_uniq_tran_enable = 0, - .gen2_tx_rate3_uniq_tran = 0x00, - .gen2_rx_tuning_enable = 0x0f, - .gen2_rx_tuning_params = 0x45, - .gen2_rx_filter_sel = 0x44, - }" # Type-A Port 2 - register "usb3_ports[1]" = "USB3_PORT_GEN2_DEFAULT(OC3)" # Type-A Port 3 - register "usb3_ports[2]" = "{ - .enable = 1, - .ocpin = OC1, - .tx_de_emp = 0x00, - .tx_downscale_amp = 0x00, - .gen2_tx_rate0_uniq_tran_enable = 0, - .gen2_tx_rate0_uniq_tran = 0x00, - .gen2_tx_rate1_uniq_tran_enable = 0, - .gen2_tx_rate1_uniq_tran = 0x00, - .gen2_tx_rate2_uniq_tran_enable = 1, - .gen2_tx_rate2_uniq_tran = 0x4c, - .gen2_tx_rate3_uniq_tran_enable = 0, - .gen2_tx_rate3_uniq_tran = 0x00, - .gen2_rx_tuning_enable = 0x0f, - .gen2_rx_tuning_params = 0x3d, - .gen2_rx_filter_sel = 0x44, - }" # Type-A Port 1 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[4]" = "{ - .enable = 1, - .ocpin = OC0, - .tx_de_emp = 0x00, - .tx_downscale_amp = 0x00, - .gen2_tx_rate0_uniq_tran_enable = 0, - .gen2_tx_rate0_uniq_tran = 0x00, - .gen2_tx_rate1_uniq_tran_enable = 0, - .gen2_tx_rate1_uniq_tran = 0x00, - .gen2_tx_rate2_uniq_tran_enable = 1, - .gen2_tx_rate2_uniq_tran = 0x4c, - .gen2_tx_rate3_uniq_tran_enable = 0, - .gen2_tx_rate3_uniq_tran = 0x00, - .gen2_rx_tuning_enable = 0x0f, - .gen2_rx_tuning_params = 0x45, - .gen2_rx_filter_sel = 0x44, - }" # Type-A Port 0 - register "usb3_ports[5]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_de_emp = 0x00, - .tx_downscale_amp = 0x00, - .gen2_tx_rate0_uniq_tran_enable = 0, - .gen2_tx_rate0_uniq_tran = 0x00, - .gen2_tx_rate1_uniq_tran_enable = 0, - .gen2_tx_rate1_uniq_tran = 0x00, - .gen2_tx_rate2_uniq_tran_enable = 1, - .gen2_tx_rate2_uniq_tran = 0x4c, - .gen2_tx_rate3_uniq_tran_enable = 0, - .gen2_tx_rate3_uniq_tran = 0x00, - .gen2_rx_tuning_enable = 0x0f, - .gen2_rx_tuning_params = 0x45, - .gen2_rx_filter_sel = 0x44, - }" # Type-A Port 4 - - # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ - USB_PORT_WAKE_ENABLE(6)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ - USB_PORT_WAKE_ENABLE(6)" - - # Enable eMMC HS400 - register "ScsEmmcHs400Enabled" = "1" - - # EMMC Tx CMD Delay - # Refer to EDS-Vol2-14.3.7. - # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" - - # EMMC TX DATA Delay 1 - # Refer to EDS-Vol2-14.3.8. - # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. - # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" - - # EMMC TX DATA Delay 2 - # Refer to EDS-Vol2-14.3.9. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. - # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" - - # EMMC RX CMD/DATA Delay 1 - # Refer to EDS-Vol2-14.3.10. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. - # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" - - # EMMC RX CMD/DATA Delay 2 - # Refer to EDS-Vol2-14.3.12. - # [17:16] stands for Rx Clock before Output Buffer, - # 00: Rx clock after output buffer, - # 01: Rx clock before output buffer, - # 10: Automatic selection based on working mode. - # 11: Reserved - # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" - - # EMMC Rx Strobe Delay - # Refer to EDS-Vol2-14.3.11. - # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. - # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" - - # Intel HDA - disable I2S Audio SSP1 and DMIC0 as kaisa variant does not have them. - register "PchHdaAudioLinkSsp1" = "0" - register "PchHdaAudioLinkDmic0" = "0" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| I2C0 | RFU | - #| I2C2 | PS175 | - #| I2C3 | MST | - #| I2C4 | Audio | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 0, - .fall_time_ns = 0, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - .i2c[4] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - }" - - # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" - # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" - # Uses CLK SRC 0 - register "PcieClkSrcUsage[0]" = "6" - register "PcieClkSrcClkReq[0]" = "0" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "vSD3_CD_B" - - # SATA port 1 Gen3 Strength - # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB - register "sata_port[1].TxGen3DeEmphEnable" = "1" - register "sata_port[1].TxGen3DeEmph" = "0x20" - - device domain 0 on - device pci 04.0 on - chip drivers/intel/dptf - ## Active Policy - register "policies.active[0]" = "{.target=DPTF_CPU, - .thresholds={TEMP_PCT(94, 0),}}" - register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, - .thresholds={TEMP_PCT(65, 90), - TEMP_PCT(61, 80), - TEMP_PCT(57, 70), - TEMP_PCT(53, 60), - TEMP_PCT(49, 50), - TEMP_PCT(45, 40), - TEMP_PCT(41, 0),}}" - - ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 68, 5000)" - - ## Critical Policy - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)" - - ## Power Limits Control - # PL1 is fixed at 15W, avg over 28-32s interval - # 15-51W PL2 in 1000mW increments, avg over 28-32s interval - register "controls.power_limits.pl1" = "{ - .min_power = 15000, - .max_power = 15000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200,}" - register "controls.power_limits.pl2" = "{ - .min_power = 15000, - .max_power = 51000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 1000,}" - - ## Charger Performance Control (Control, mA) - register "controls.charger_perf[0]" = "{ 255, 1700 }" - register "controls.charger_perf[1]" = "{ 24, 1500 }" - register "controls.charger_perf[2]" = "{ 16, 1000 }" - register "controls.charger_perf[3]" = "{ 8, 500 }" - - ## Fan Performance Control (Percent, Speed, Noise, Power) - register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" - register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" - register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" - register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" - register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" - register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" - register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" - register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" - register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" - register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" - - # Fan options - register "options.fan.fine_grained_control" = "1" - register "options.fan.step_size" = "2" - - device generic 0 on end - end - end # DPTF 0x1903 - device pci 14.0 on - chip drivers/usb/acpi - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Left"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 3)" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Right"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Right"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 2.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Middle"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Left"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 2.5 on end - end - chip drivers/usb/acpi - device usb 2.6 off end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Left"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Right"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Right"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 3)" - device usb 3.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Left"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 3.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Middle"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 3.5 on end - end - end - end - end # USB xHCI - device pci 15.0 off - # RFU - Reserved for Future Use. - end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 on - chip drivers/i2c/generic - register "hid" = ""1AF80175"" - register "name" = ""PS17"" - register "desc" = ""Parade PS175"" - device i2c 4a on end - end - end # I2C #2, PCON PS175. - device pci 15.3 on - chip drivers/i2c/generic - register "hid" = ""10EC2142"" - register "name" = ""RTD2"" - register "desc" = ""Realtek RTD2142"" - device i2c 4a on end - end - end # I2C #3, Realtek RTD2142. - device pci 16.0 on end # Management Engine Interface 1 - device pci 19.0 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" - register "property_count" = "1" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on end - end - end #I2C #4 - device pci 1a.0 on end # eMMC - device pci 1c.6 on - chip drivers/net - register "customized_leds" = "0x05af" - register "wake" = "GPE0_DW1_07" # GPP_C7 - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" - register "stop_delay_ms" = "12" # NIC needs time to quiesce - register "stop_off_delay_ms" = "1" - register "has_power_resource" = "1" - register "device_index" = "0" - device pci 00.0 on end - end - register "PcieRpSlotImplemented[6]" = "1" - end # RTL8111H Ethernet NIC - device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) - register "PcieRpSlotImplemented[10]" = "1" - end - device pci 1e.3 off end # GSPI #1 - end - - # VR Settings Configuration for 4 Domains - #+----------------+-------+-------+-------+-------+ - #| Domain/Setting | SA | IA | GTUS | GTS | - #+----------------+-------+-------+-------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | - #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | - #+----------------+-------+-------+-------+-------+ - #Note: IccMax settings are moved to SoC code - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 1004, - .dc_loadline = 1004, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 181, - .dc_loadline = 181, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 319, - .dc_loadline = 319, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 319, - .dc_loadline = 319, - }" - -end diff --git a/src/mainboard/google/hatch/variants/moonbuggy/Makefile.inc b/src/mainboard/google/hatch/variants/moonbuggy/Makefile.inc deleted file mode 100644 index 3b5b7d000d..0000000000 --- a/src/mainboard/google/hatch/variants/moonbuggy/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ramstage-y += gpio.c -bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/moonbuggy/gpio.c b/src/mainboard/google/hatch/variants/moonbuggy/gpio.c deleted file mode 100644 index d8f392028d..0000000000 --- a/src/mainboard/google/hatch/variants/moonbuggy/gpio.c +++ /dev/null @@ -1,157 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <commonlib/helpers.h> - -static const struct pad_config gpio_table[] = { - /* A16 : SD_OC_ODL */ - PAD_CFG_GPI(GPP_A16, NONE, DEEP), - /* A18 : LAN_PE_ISOLATE_ODL */ - PAD_CFG_GPO(GPP_A18, 1, DEEP), - /* A19 : PCH_PCON0_PDB_ODL */ - PAD_CFG_GPO(GPP_A19, 1, DEEP), - /* A20 : LAN_I350_WAKE# */ - PAD_CFG_GPI_IRQ_WAKE(GPP_A20, NONE, DEEP, LEVEL, INVERT), - /* A23 : M2_WLAN_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), - - /* B5 : LAN_CLKREQ_ODL */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), - /* B6 : M2_SSD_CLKREQ_ODL */ - PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), - /* B7 : M2_TPU0_CLKREQ_ODL */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), - /* B8 : CLK_PCIE_REQ3 (not connected) */ - PAD_NC(GPP_B8, NONE), - /* B9 : M2_TPU1_CLKREQ_ODL */ - PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), - /* B10 : M2_WLAN_CLKREQ_ODL */ - PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), - - /* C0 : SMBCLK */ - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), - /* C1 : SMBDATA */ - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - /* C3 : PCH_MBCLK1_R (i350) */ - PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), - /* C4 : PCH_MBDAT1_R (i350) */ - PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), - /* C6 : M2_WLAN_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), - /* C7 : LAN_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), - /* C10 : PCH_PCON_RST_ODL */ - PAD_CFG_GPO(GPP_C10, 1, DEEP), - /* C11 : PCH_PCON1_PDB_ODL */ - PAD_CFG_GPO(GPP_C11, 1, DEEP), - /* C12 : PCH_UART1_RX_ADB_TX */ - PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), - /* C13 : PCH_UART1_TX_ADB_RX */ - PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), - /* C15 : WLAN_OFF_L */ - PAD_CFG_GPO(GPP_C15, 1, DEEP), - /* C16 : PCH_I2C_RFU_SDA (NC) */ - PAD_NC(GPP_C16, NONE), - /* C17 : PCH_I2C_RFU_SCL (NC) */ - PAD_NC(GPP_C17, NONE), - /* C18 : EC_I2C_HDMI_RE_SCL */ - PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), - /* C19 : EC_12C_HDMI_RE_SDA */ - PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), - - /* D1 : REC_MODE */ - PAD_CFG_GPO(GPP_D1, 1, DEEP), - /* D2 : DEV_MODE_CTRL */ - PAD_CFG_GPO(GPP_D2, 1, DEEP), - /* D3 : BOOT_IND */ - PAD_CFG_GPI(GPP_D3, NONE, DEEP), - /* D14 : EC_PCH_INT_L */ - PAD_CFG_GPI_APIC(GPP_D14, NONE, PLTRST, LEVEL, INVERT), - /* D21 : BOOT_SEL_N */ - PAD_CFG_GPO(GPP_D21, 1, DEEP), - /* D22 : QSPI_MR_N */ - PAD_CFG_GPO(GPP_D22, 1, DEEP), - /* D23 : Not connected */ - PAD_NC(GPP_D23, NONE), - - /* E2 : Not connected */ - PAD_NC(GPP_E2, NONE), - /* E3 : TPU_BOOT_DELAY_PIN40 */ - PAD_CFG_GPO(GPP_E3, 1, DEEP), - /* E7 : TPU_BOOT_DELAY_PIN42 */ - PAD_CFG_GPO(GPP_E7, 1, DEEP), - /* E9 : PU 10K to PP3300_SOC_A */ - PAD_NC(GPP_E9, NONE), - /* E10 : USB_A1_OC_ODL */ - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), - /* E11 : PU 10K to PP3300_SOC_A */ - PAD_NC(GPP_E11, NONE), - /* E12 : PU 10K to PP3300_SOC_A */ - PAD_NC(GPP_E12, NONE), - /* E15 : PCH_TYPEC_UPFB */ - PAD_CFG_GPI(GPP_E15, NONE, DEEP), - - /* H0 : Not connected */ - PAD_NC(GPP_H0, NONE), - /* H4 : PCH_I2C_PCON_SDA */ - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* H5 : PCH_I2C_PCON_SCL */ - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* H6 : PCH_I2C_TPU_SDA */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), - /* H7 : PCH_I2C_TPU_SCL */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), - /* H8 : Not connected */ - PAD_NC(GPP_H8, NONE), - /* H9 : Not connected */ - PAD_NC(GPP_H9, NONE), - /* H22 : PWM_PP3300_BIOZZER */ - PAD_CFG_GPO(GPP_H22, 0, DEEP), -}; - -const struct pad_config *override_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* B14 : GPP_B14_STRAP */ - PAD_NC(GPP_B14, NONE), - /* B22 : GPP_B22_STRAP */ - PAD_NC(GPP_B22, NONE), - /* E19 : GPP_E19_STRAP */ - PAD_NC(GPP_E19, NONE), - /* E21 : GPP_E21_STRAP */ - PAD_NC(GPP_E21, NONE), - /* B15 : H1_SLAVE_SPI_CS_L */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* B16 : H1_SLAVE_SPI_CLK */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* B17 : H1_SLAVE_SPI_MISO_R */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* B18 : H1_SLAVE_SPI_MOSI_R */ - PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* C14 : BT_DISABLE_L */ - PAD_CFG_GPO(GPP_C14, 0, DEEP), - /* C20 : PCH_WP_OD */ - PAD_CFG_GPI(GPP_C20, NONE, DEEP), - /* C21 : H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), - /* C22 : EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_C22, NONE, DEEP), - /* C23 : WLAN_PE_RST# */ - PAD_CFG_GPO(GPP_C23, 1, DEEP), - /* E1 : M2_SSD_PEDET */ - PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), - /* E5 : SATA_DEVSLP1 */ - PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), -}; - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} diff --git a/src/mainboard/google/hatch/variants/moonbuggy/include/variant/ec.h b/src/mainboard/google/hatch/variants/moonbuggy/include/variant/ec.h deleted file mode 100644 index 59fb3783c5..0000000000 --- a/src/mainboard/google/hatch/variants/moonbuggy/include/variant/ec.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_EC_H -#define VARIANT_EC_H - -#include <puff/ec.h> - -#endif diff --git a/src/mainboard/google/hatch/variants/moonbuggy/include/variant/gpio.h b/src/mainboard/google/hatch/variants/moonbuggy/include/variant/gpio.h deleted file mode 100644 index 9dd243400d..0000000000 --- a/src/mainboard/google/hatch/variants/moonbuggy/include/variant/gpio.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include <baseboard/gpio.h> - -#undef EC_SYNC_IRQ -#define EC_SYNC_IRQ GPP_D14_IRQ - -#endif diff --git a/src/mainboard/google/hatch/variants/moonbuggy/overridetree.cb b/src/mainboard/google/hatch/variants/moonbuggy/overridetree.cb deleted file mode 100644 index 1049805700..0000000000 --- a/src/mainboard/google/hatch/variants/moonbuggy/overridetree.cb +++ /dev/null @@ -1,535 +0,0 @@ -chip soc/intel/cannonlake - # Auto-switch between X4 NVMe and X2 NVMe. - register "TetonGlacierMode" = "1" - - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - [PchSerialIoIndexSPI0] = PchSerialIoPci, - [PchSerialIoIndexSPI1] = PchSerialIoPci, - [PchSerialIoIndexSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoSkipInit, - [PchSerialIoIndexUART1] = PchSerialIoPci, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - - # USB configuration - register "usb2_ports[0]" = "{ - .enable = 1, - .ocpin = OC2, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_11P25MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 2 - register "usb2_ports[1]" = "{ - .enable = 1, - .ocpin = OC1, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 1 - register "usb2_ports[2]" = "{ - .enable = 1, - .ocpin = OC3, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 3 - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port - register "usb2_ports[4]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 4 - register "usb2_ports[5]" = "{ - .enable = 1, - .ocpin = OC0, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A port 0 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" - register "usb2_ports[9]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # BT - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 - - # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ - USB_PORT_WAKE_ENABLE(6)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ - USB_PORT_WAKE_ENABLE(6)" - - # Enable eMMC HS400 - register "ScsEmmcHs400Enabled" = "1" - - # EMMC Tx CMD Delay - # Refer to EDS-Vol2-14.3.7. - # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" - - # EMMC TX DATA Delay 1 - # Refer to EDS-Vol2-14.3.8. - # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. - # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" - - # EMMC TX DATA Delay 2 - # Refer to EDS-Vol2-14.3.9. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. - # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" - - # EMMC RX CMD/DATA Delay 1 - # Refer to EDS-Vol2-14.3.10. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. - # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" - - # EMMC RX CMD/DATA Delay 2 - # Refer to EDS-Vol2-14.3.12. - # [17:16] stands for Rx Clock before Output Buffer, - # 00: Rx clock after output buffer, - # 01: Rx clock before output buffer, - # 10: Automatic selection based on working mode. - # 11: Reserved - # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" - - # EMMC Rx Strobe Delay - # Refer to EDS-Vol2-14.3.11. - # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. - # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" - - # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. - register "PchHdaAudioLinkSsp1" = "0" - register "PchHdaAudioLinkDmic0" = "0" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| I2C0 | RFU | - #| I2C2 | PS175 | - #| I2C3 | MST | - #| I2C4 | Audio | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 0, - .fall_time_ns = 0, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - .i2c[4] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - }" - - # PCIe root port 7 for LAN - register "PcieRpEnable[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" - # Uses CLK SRC 0 - register "PcieClkSrcUsage[0]" = "6" - register "PcieClkSrcClkReq[0]" = "0" - - # PCIe root port 8 for WLAN - register "PcieRpEnable[7]" = "1" - register "PcieRpLtrEnable[7]" = "1" - # Uses CLK SRC 5 - register "PcieClkSrcUsage[5]" = "7" - register "PcieClkSrcClkReq[5]" = "5" - - # PCIe root port 9 for SSD (PCIe Lanes 11, 12) - register "PcieRpEnable[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" - # RP 9 uses CLK SRC 1 - register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcClkReq[1]" = "1" - - # PCIe root port 10 disabled - register "PcieRpEnable[9]" = "0" - - # PCIe root port 11 TPU1 - register "PcieRpEnable[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" - # RP 11 uses CLK SRC 1 - register "PcieClkSrcUsage[4]" = "10" - register "PcieClkSrcClkReq[4]" = "4" - - # PCIe root port 12 TPU0 - register "PcieRpEnable[11]" = "1" - register "PcieRpLtrEnable[11]" = "1" - # RP 11 uses CLK SRC 1 - register "PcieClkSrcUsage[2]" = "11" - register "PcieClkSrcClkReq[2]" = "2" - - # PCIe port 13 for i350 NIC (x4) - register "PcieRpEnable[12]" = "1" - register "PcieRpLtrEnable[12]" = "1" - # RP 13 uses CLK SRC 3 - register "PcieClkSrcUsage[3]" = "12" - # RP 13 does not use a source clock request line - # NOTE: Any value other than a valid source-clock-request (0-5) is - # effectively "not connected" - register "PcieClkSrcClkReq[3]" = "0xFF" - # Disable the remaining ports 14-16 - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "vSD3_CD_B" - - # SATA port 1 Gen3 Strength - # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB - register "sata_port[1].TxGen3DeEmphEnable" = "1" - register "sata_port[1].TxGen3DeEmph" = "0x20" - - device domain 0 on - device pci 04.0 on - chip drivers/intel/dptf - ## Active Policy - register "policies.active[0]" = "{.target=DPTF_CPU, - .thresholds={TEMP_PCT(94, 0),}}" - register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, - .thresholds={TEMP_PCT(72, 90), - TEMP_PCT(68, 80), - TEMP_PCT(62, 70), - TEMP_PCT(54, 60), - TEMP_PCT(46, 50), - TEMP_PCT(39, 40),}}" - - ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 6000)" - - ## Critical Policy - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN)" - - ## Power Limits Control - # PL1 is fixed at 15W, avg over 28-32s interval - # 51-51W PL2 in 1000mW increments, avg over 28-32s interval - register "controls.power_limits.pl1" = "{ - .min_power = 15000, - .max_power = 15000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 125,}" - register "controls.power_limits.pl2" = "{ - .min_power = 51000, - .max_power = 51000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 1000,}" - - ## Charger Performance Control (Control, mA) - register "controls.charger_perf[0]" = "{ 255, 1700 }" - register "controls.charger_perf[1]" = "{ 24, 1500 }" - register "controls.charger_perf[2]" = "{ 16, 1000 }" - register "controls.charger_perf[3]" = "{ 8, 500 }" - - ## Fan Performance Control (Percent, Speed, Noise, Power) - register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" - register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" - register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" - register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" - register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" - register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" - register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" - register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" - register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" - register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" - - # Fan options - register "options.fan.fine_grained_control" = "1" - register "options.fan.step_size" = "2" - - device generic 0 on end - end - end # DPTF 0x1903 - device pci 14.0 on - chip drivers/usb/acpi - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Left"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 3)" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Right"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Right"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 2.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Middle"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Left"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 2.5 on end - end - chip drivers/usb/acpi - device usb 2.6 off end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Left"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Right"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Right"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 3)" - device usb 3.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Left"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 3.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Middle"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 3.5 on end - end - end - end - end # USB xHCI - device pci 15.0 off - # RFU - Reserved for Future Use. - end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 on - chip drivers/i2c/generic - register "hid" = ""1AF80175"" - register "name" = ""PS17"" - register "desc" = ""Parade PS175"" - device i2c 4a on end - end - end # I2C #2, PCON PS175. - device pci 15.3 on - chip drivers/i2c/generic - register "hid" = ""10EC2142"" - register "name" = ""RTD2"" - register "desc" = ""Realtek RTD2142"" - device i2c 4a on end - end - end # I2C #3, Realtek RTD2142. - device pci 16.0 on end # Management Engine Interface 1 - device pci 19.0 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" - register "property_count" = "1" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on end - end - end #I2C #4 - device pci 1a.0 off end # eMMC - device pci 1c.6 on # PCI Root Port 7 (LAN) - chip drivers/net # RTL8111H Ethernet NIC - register "customized_leds" = "0x05af" - register "wake" = "GPE0_DW1_07" # GPP_C7 - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" - register "stop_delay_ms" = "12" # NIC needs time to quiesce - register "stop_off_delay_ms" = "1" - register "has_power_resource" = "1" - register "device_index" = "0" - device pci 00.0 on end - end - end - device pci 1c.7 on # PCI Root Port 8 (WLAN) - register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot - end - device pci 1d.0 on # PCI Root Port 9 (TPU) - register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot - end - device pci 1d.1 off end # PCI Root Port 10 (Not connected) - device pci 1d.2 on end # PCI Root Port 11 (TPU1) - register "PcieRpSlotImplemented[10]" = "1" # M.2 Slot - device pci 1d.3 on end # PCI Root Port 12 (TPU0) - register "PcieRpSlotImplemented[11]" = "1" # M.2 Slot - device pci 1d.4 on # PCI Root Port 13 (X4 i350 NIC) - register "PcieRpSlotImplemented[12]" = "0" # Built-in - end - device pci 1d.5 on end # PCI Root Port 14 (non-root) - device pci 1d.6 on end # PCI Root Port 15 (non-root) - device pci 1d.7 on end # PCI Root Port 16 (non-root) - device pci 1e.0 on end # UART #0 - device pci 1e.1 on end # UART #1 - device pci 1e.3 off end # GSPI #1 - end - - # VR Settings Configuration for 4 Domains - #+----------------+-------+-------+-------+-------+ - #| Domain/Setting | SA | IA | GTUS | GTS | - #+----------------+-------+-------+-------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | - #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | - #+----------------+-------+-------+-------+-------+ - #Note: IccMax settings are moved to SoC code - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 1004, - .dc_loadline = 1004, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 181, - .dc_loadline = 181, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 319, - .dc_loadline = 319, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 319, - .dc_loadline = 319, - }" - -end diff --git a/src/mainboard/google/hatch/variants/noibat/Makefile.inc b/src/mainboard/google/hatch/variants/noibat/Makefile.inc deleted file mode 100644 index 3b5b7d000d..0000000000 --- a/src/mainboard/google/hatch/variants/noibat/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ramstage-y += gpio.c -bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/noibat/data.vbt b/src/mainboard/google/hatch/variants/noibat/data.vbt Binary files differdeleted file mode 100644 index cda1c25d7d..0000000000 --- a/src/mainboard/google/hatch/variants/noibat/data.vbt +++ /dev/null diff --git a/src/mainboard/google/hatch/variants/noibat/gpio.c b/src/mainboard/google/hatch/variants/noibat/gpio.c deleted file mode 100644 index 996edc4fc7..0000000000 --- a/src/mainboard/google/hatch/variants/noibat/gpio.c +++ /dev/null @@ -1,117 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <commonlib/helpers.h> - -static const struct pad_config gpio_table[] = { - /* A16 : SD_OC_ODL */ - PAD_CFG_GPI(GPP_A16, NONE, DEEP), - /* A18 : LAN_PE_ISOLATE_ODL */ - PAD_CFG_GPO(GPP_A18, 1, DEEP), - /* A23 : M2_WLAN_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), - - /* B5 : LAN_CLKREQ_ODL */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), - - /* C0 : SMBCLK */ - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), - /* C1 : SMBDATA */ - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - /* C6: M2_WLAN_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), - /* C7 : LAN_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), - /* C10 : PCH_PCON_RST_ODL */ - PAD_CFG_GPO(GPP_C10, 1, DEEP), - /* C11 : PCH_PCON_PDB_ODL */ - PAD_CFG_GPO(GPP_C11, 1, DEEP), - /* C15 : WLAN_OFF_L */ - PAD_CFG_GPO(GPP_C15, 1, DEEP), - - /* E2 : EN_PP_MST_OD */ - PAD_CFG_GPO(GPP_E2, 1, DEEP), - /* E9 : USB_A0_OC_ODL */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - /* E10 : USB_A1_OC_ODL */ - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), - - /* F11 : EMMC_CMD */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), - /* F12 : EMMC_DATA0 */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), - /* F13 : EMMC_DATA1 */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), - /* F14 : EMMC_DATA2 */ - PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), - /* F15 : EMMC_DATA3 */ - PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), - /* F16 : EMMC_DATA4 */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), - /* F17 : EMMC_DATA5 */ - PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), - /* F18 : EMMC_DATA6 */ - PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), - /* F19 : EMMC_DATA7 */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - /* F20 : EMMC_RCLK */ - PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), - /* F21 : EMMC_CLK */ - PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), - /* F22 : EMMC_RST_L */ - PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), - - /* H4: PCH_I2C_PCON_SDA */ - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* H5: PCH_I2C_PCON_SCL */ - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* H22 : PWM_PP3300_BIOZZER */ - PAD_CFG_GPO(GPP_H22, 0, DEEP), -}; - -const struct pad_config *override_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* B14 : GPP_B14_STRAP */ - PAD_NC(GPP_B14, NONE), - /* B22 : GPP_B22_STRAP */ - PAD_NC(GPP_B22, NONE), - /* E19 : GPP_E19_STRAP */ - PAD_NC(GPP_E19, NONE), - /* E21 : GPP_E21_STRAP */ - PAD_NC(GPP_E21, NONE), - /* B15 : H1_SLAVE_SPI_CS_L */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* B16 : H1_SLAVE_SPI_CLK */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* B17 : H1_SLAVE_SPI_MISO_R */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* B18 : H1_SLAVE_SPI_MOSI_R */ - PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* C14 : BT_DISABLE_L */ - PAD_CFG_GPO(GPP_C14, 0, DEEP), - /* PCH_WP_OD */ - PAD_CFG_GPI(GPP_C20, NONE, DEEP), - /* C21 : H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), - /* C22 : EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_C22, NONE, DEEP), - /* C23 : WLAN_PE_RST# */ - PAD_CFG_GPO(GPP_C23, 1, DEEP), - /* E1 : M2_SSD_PEDET */ - PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), - /* E5 : SATA_DEVSLP1 */ - PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), -}; - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} diff --git a/src/mainboard/google/hatch/variants/noibat/include/variant/ec.h b/src/mainboard/google/hatch/variants/noibat/include/variant/ec.h deleted file mode 100644 index 59fb3783c5..0000000000 --- a/src/mainboard/google/hatch/variants/noibat/include/variant/ec.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_EC_H -#define VARIANT_EC_H - -#include <puff/ec.h> - -#endif diff --git a/src/mainboard/google/hatch/variants/noibat/include/variant/gpio.h b/src/mainboard/google/hatch/variants/noibat/include/variant/gpio.h deleted file mode 100644 index 79a141008f..0000000000 --- a/src/mainboard/google/hatch/variants/noibat/include/variant/gpio.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include <baseboard/gpio.h> - -#endif diff --git a/src/mainboard/google/hatch/variants/noibat/overridetree.cb b/src/mainboard/google/hatch/variants/noibat/overridetree.cb deleted file mode 100644 index cf6046224c..0000000000 --- a/src/mainboard/google/hatch/variants/noibat/overridetree.cb +++ /dev/null @@ -1,458 +0,0 @@ -chip soc/intel/cannonlake - register "power_limits_config" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 51, - }" - - # Auto-switch between X4 NVMe and X2 NVMe. - register "TetonGlacierMode" = "1" - - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - [PchSerialIoIndexSPI0] = PchSerialIoPci, - [PchSerialIoIndexSPI1] = PchSerialIoPci, - [PchSerialIoIndexSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoSkipInit, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - - # USB configuration - register "usb2_ports[0]" = "{ - .enable = 1, - .ocpin = OC2, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_11P25MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 2 - register "usb2_ports[1]" = "{ - .enable = 1, - .ocpin = OC1, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 1 - register "usb2_ports[2]" = "{ - .enable = 1, - .ocpin = OC3, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 3 - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port - register "usb2_ports[5]" = "{ - .enable = 1, - .ocpin = OC0, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A port 0 - register "usb2_ports[9]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # BT - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 - - # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(6)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5)" - - # Enable eMMC HS400 - register "ScsEmmcHs400Enabled" = "1" - - # EMMC Tx CMD Delay - # Refer to EDS-Vol2-14.3.7. - # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" - - # EMMC TX DATA Delay 1 - # Refer to EDS-Vol2-14.3.8. - # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. - # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" - - # EMMC TX DATA Delay 2 - # Refer to EDS-Vol2-14.3.9. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. - # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" - - # EMMC RX CMD/DATA Delay 1 - # Refer to EDS-Vol2-14.3.10. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. - # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" - - # EMMC RX CMD/DATA Delay 2 - # Refer to EDS-Vol2-14.3.12. - # [17:16] stands for Rx Clock before Output Buffer, - # 00: Rx clock after output buffer, - # 01: Rx clock before output buffer, - # 10: Automatic selection based on working mode. - # 11: Reserved - # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" - - # EMMC Rx Strobe Delay - # Refer to EDS-Vol2-14.3.11. - # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. - # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" - - # Intel HDA - disable I2S Audio SSP1 and DMIC0 as noibat variant does not have them. - register "PchHdaAudioLinkSsp1" = "0" - register "PchHdaAudioLinkDmic0" = "0" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| I2C0 | RFU | - #| I2C2 | PS175 | - #| I2C3 | MST | - #| I2C4 | Audio | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 0, - .fall_time_ns = 0, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - .i2c[4] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - }" - - # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" - # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" - # Uses CLK SRC 0 - register "PcieClkSrcUsage[0]" = "6" - register "PcieClkSrcClkReq[0]" = "0" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "vSD3_CD_B" - - # SATA port 1 Gen3 Strength - # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB - register "sata_port[1].TxGen3DeEmphEnable" = "1" - register "sata_port[1].TxGen3DeEmph" = "0x20" - - device domain 0 on - device pci 04.0 on - chip drivers/intel/dptf - ## Active Policy - register "policies.active[0]" = "{.target=DPTF_CPU, - .thresholds={TEMP_PCT(94, 0),}}" - register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, - .thresholds={TEMP_PCT(65, 90), - TEMP_PCT(52, 80), - TEMP_PCT(50, 70), - TEMP_PCT(48, 60), - TEMP_PCT(46, 50), - TEMP_PCT(44, 40), - TEMP_PCT(42, 0),}}" - - ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 68, 5000)" - - ## Critical Policy - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)" - - ## Power Limits Control - # PL1 is fixed at 15W, avg over 28-32s interval - # 15-51W PL2 in 1000mW increments, avg over 28-32s interval - register "controls.power_limits.pl1" = "{ - .min_power = 15000, - .max_power = 15000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200,}" - register "controls.power_limits.pl2" = "{ - .min_power = 15000, - .max_power = 51000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 1000,}" - - ## Charger Performance Control (Control, mA) - register "controls.charger_perf[0]" = "{ 255, 1700 }" - register "controls.charger_perf[1]" = "{ 24, 1500 }" - register "controls.charger_perf[2]" = "{ 16, 1000 }" - register "controls.charger_perf[3]" = "{ 8, 500 }" - - ## Fan Performance Control (Percent, Speed, Noise, Power) - register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" - register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" - register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" - register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" - register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" - register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" - register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" - register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" - register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" - register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" - - # Fan options - register "options.fan.fine_grained_control" = "1" - register "options.fan.step_size" = "2" - - device generic 0 on end - end - end # DPTF 0x1903 - device pci 14.0 on - chip drivers/usb/acpi - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Left"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 3)" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Right"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Right"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 2.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Left"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 2.5 on end - end - chip drivers/usb/acpi - device usb 2.6 off end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Left"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Right"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Right"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 3)" - device usb 3.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Left"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 3.4 on end - end - end - end - end # USB xHCI - device pci 15.0 off - # RFU - Reserved for Future Use. - end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 on - chip drivers/i2c/generic - register "hid" = ""1AF80175"" - register "name" = ""PS17"" - register "desc" = ""Parade PS175"" - device i2c 4a on end - end - end # I2C #2, PCON PS175. - device pci 15.3 on - chip drivers/i2c/generic - register "hid" = ""10EC2142"" - register "name" = ""RTD2"" - register "desc" = ""Realtek RTD2142"" - device i2c 4a on end - end - end # I2C #3, Realtek RTD2142. - device pci 16.0 on end # Management Engine Interface 1 - device pci 19.0 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" - register "property_count" = "1" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on end - end - end #I2C #4 - device pci 1a.0 on end # eMMC - device pci 1c.6 on - chip drivers/net - register "customized_leds" = "0x05af" - register "wake" = "GPE0_DW1_07" # GPP_C7 - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" - register "stop_delay_ms" = "12" # NIC needs time to quiesce - register "stop_off_delay_ms" = "1" - register "has_power_resource" = "1" - register "device_index" = "0" - device pci 00.0 on end - end - register "PcieRpSlotImplemented[6]" = "1" - end # RTL8111H Ethernet NIC - device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) - register "PcieRpSlotImplemented[10]" = "1" - end - device pci 1e.3 off end # GSPI #1 - end - - # VR Settings Configuration for 4 Domains - #+----------------+-------+-------+-------+-------+ - #| Domain/Setting | SA | IA | GTUS | GTS | - #+----------------+-------+-------+-------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | - #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | - #+----------------+-------+-------+-------+-------+ - #Note: IccMax settings are moved to SoC code - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 1004, - .dc_loadline = 1004, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 181, - .dc_loadline = 181, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 319, - .dc_loadline = 319, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 319, - .dc_loadline = 319, - }" - -end diff --git a/src/mainboard/google/hatch/variants/puff/Makefile.inc b/src/mainboard/google/hatch/variants/puff/Makefile.inc deleted file mode 100644 index 3b5b7d000d..0000000000 --- a/src/mainboard/google/hatch/variants/puff/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ramstage-y += gpio.c -bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/puff/data.vbt b/src/mainboard/google/hatch/variants/puff/data.vbt Binary files differdeleted file mode 100644 index cda1c25d7d..0000000000 --- a/src/mainboard/google/hatch/variants/puff/data.vbt +++ /dev/null diff --git a/src/mainboard/google/hatch/variants/puff/gpio.c b/src/mainboard/google/hatch/variants/puff/gpio.c deleted file mode 100644 index 996edc4fc7..0000000000 --- a/src/mainboard/google/hatch/variants/puff/gpio.c +++ /dev/null @@ -1,117 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <commonlib/helpers.h> - -static const struct pad_config gpio_table[] = { - /* A16 : SD_OC_ODL */ - PAD_CFG_GPI(GPP_A16, NONE, DEEP), - /* A18 : LAN_PE_ISOLATE_ODL */ - PAD_CFG_GPO(GPP_A18, 1, DEEP), - /* A23 : M2_WLAN_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), - - /* B5 : LAN_CLKREQ_ODL */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), - - /* C0 : SMBCLK */ - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), - /* C1 : SMBDATA */ - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - /* C6: M2_WLAN_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), - /* C7 : LAN_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), - /* C10 : PCH_PCON_RST_ODL */ - PAD_CFG_GPO(GPP_C10, 1, DEEP), - /* C11 : PCH_PCON_PDB_ODL */ - PAD_CFG_GPO(GPP_C11, 1, DEEP), - /* C15 : WLAN_OFF_L */ - PAD_CFG_GPO(GPP_C15, 1, DEEP), - - /* E2 : EN_PP_MST_OD */ - PAD_CFG_GPO(GPP_E2, 1, DEEP), - /* E9 : USB_A0_OC_ODL */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - /* E10 : USB_A1_OC_ODL */ - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), - - /* F11 : EMMC_CMD */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), - /* F12 : EMMC_DATA0 */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), - /* F13 : EMMC_DATA1 */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), - /* F14 : EMMC_DATA2 */ - PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), - /* F15 : EMMC_DATA3 */ - PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), - /* F16 : EMMC_DATA4 */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), - /* F17 : EMMC_DATA5 */ - PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), - /* F18 : EMMC_DATA6 */ - PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), - /* F19 : EMMC_DATA7 */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - /* F20 : EMMC_RCLK */ - PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), - /* F21 : EMMC_CLK */ - PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), - /* F22 : EMMC_RST_L */ - PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), - - /* H4: PCH_I2C_PCON_SDA */ - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* H5: PCH_I2C_PCON_SCL */ - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* H22 : PWM_PP3300_BIOZZER */ - PAD_CFG_GPO(GPP_H22, 0, DEEP), -}; - -const struct pad_config *override_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* B14 : GPP_B14_STRAP */ - PAD_NC(GPP_B14, NONE), - /* B22 : GPP_B22_STRAP */ - PAD_NC(GPP_B22, NONE), - /* E19 : GPP_E19_STRAP */ - PAD_NC(GPP_E19, NONE), - /* E21 : GPP_E21_STRAP */ - PAD_NC(GPP_E21, NONE), - /* B15 : H1_SLAVE_SPI_CS_L */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* B16 : H1_SLAVE_SPI_CLK */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* B17 : H1_SLAVE_SPI_MISO_R */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* B18 : H1_SLAVE_SPI_MOSI_R */ - PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* C14 : BT_DISABLE_L */ - PAD_CFG_GPO(GPP_C14, 0, DEEP), - /* PCH_WP_OD */ - PAD_CFG_GPI(GPP_C20, NONE, DEEP), - /* C21 : H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), - /* C22 : EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_C22, NONE, DEEP), - /* C23 : WLAN_PE_RST# */ - PAD_CFG_GPO(GPP_C23, 1, DEEP), - /* E1 : M2_SSD_PEDET */ - PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), - /* E5 : SATA_DEVSLP1 */ - PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), -}; - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h deleted file mode 100644 index 59fb3783c5..0000000000 --- a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_EC_H -#define VARIANT_EC_H - -#include <puff/ec.h> - -#endif diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h b/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h deleted file mode 100644 index 79a141008f..0000000000 --- a/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include <baseboard/gpio.h> - -#endif diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb deleted file mode 100644 index 0d9bf7237e..0000000000 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ /dev/null @@ -1,482 +0,0 @@ -chip soc/intel/cannonlake - - # Auto-switch between X4 NVMe and X2 NVMe. - register "TetonGlacierMode" = "1" - - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - [PchSerialIoIndexSPI0] = PchSerialIoPci, - [PchSerialIoIndexSPI1] = PchSerialIoPci, - [PchSerialIoIndexSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoSkipInit, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - - # USB configuration - # NOTE: This only applies to Puff, - # usb2_ports[1] and usb2_ports[3] were swapped on - # reference schematics after Puff has been built. - register "usb2_ports[0]" = "{ - .enable = 1, - .ocpin = OC2, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_11P25MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 2 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port - register "usb2_ports[2]" = "{ - .enable = 1, - .ocpin = OC3, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 3 - register "usb2_ports[3]" = "{ - .enable = 1, - .ocpin = OC1, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 1 - register "usb2_ports[4]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 4 - register "usb2_ports[5]" = "{ - .enable = 1, - .ocpin = OC0, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A port 0 - register "usb2_ports[9]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # BT - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 - - # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(4) | \ - USB_PORT_WAKE_ENABLE(5) | \ - USB_PORT_WAKE_ENABLE(6)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ - USB_PORT_WAKE_ENABLE(6)" - - # Enable eMMC HS400 - register "ScsEmmcHs400Enabled" = "1" - - # EMMC Tx CMD Delay - # Refer to EDS-Vol2-14.3.7. - # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" - - # EMMC TX DATA Delay 1 - # Refer to EDS-Vol2-14.3.8. - # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. - # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" - - # EMMC TX DATA Delay 2 - # Refer to EDS-Vol2-14.3.9. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. - # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" - - # EMMC RX CMD/DATA Delay 1 - # Refer to EDS-Vol2-14.3.10. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. - # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" - - # EMMC RX CMD/DATA Delay 2 - # Refer to EDS-Vol2-14.3.12. - # [17:16] stands for Rx Clock before Output Buffer, - # 00: Rx clock after output buffer, - # 01: Rx clock before output buffer, - # 10: Automatic selection based on working mode. - # 11: Reserved - # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" - - # EMMC Rx Strobe Delay - # Refer to EDS-Vol2-14.3.11. - # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. - # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" - - # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. - register "PchHdaAudioLinkSsp1" = "0" - register "PchHdaAudioLinkDmic0" = "0" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| I2C0 | RFU | - #| I2C2 | PS175 | - #| I2C3 | MST | - #| I2C4 | Audio | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 0, - .fall_time_ns = 0, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - .i2c[4] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - }" - - # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" - # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" - # Uses CLK SRC 0 - register "PcieClkSrcUsage[0]" = "6" - register "PcieClkSrcClkReq[0]" = "0" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "vSD3_CD_B" - - # SATA port 1 Gen3 Strength - # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB - register "sata_port[1].TxGen3DeEmphEnable" = "1" - register "sata_port[1].TxGen3DeEmph" = "0x20" - - device domain 0 on - device pci 04.0 on - chip drivers/intel/dptf - ## Active Policy - register "policies.active[0]" = "{.target=DPTF_CPU, - .thresholds={TEMP_PCT(90, 85), - TEMP_PCT(85, 75), - TEMP_PCT(80, 65), - TEMP_PCT(75, 55), - TEMP_PCT(70, 45),}}" - register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, - .thresholds={TEMP_PCT(50, 85), - TEMP_PCT(47, 75), - TEMP_PCT(45, 65), - TEMP_PCT(42, 55), - TEMP_PCT(39, 45),}}" - - ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" - - ## Critical Policy - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" - - ## Power Limits Control - # PL1 is fixed at 15W, avg over 28-32s interval - # 25-64W PL2 in 1000mW increments, avg over 28-32s interval - register "controls.power_limits.pl1" = "{ - .min_power = 15000, - .max_power = 15000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200,}" - register "controls.power_limits.pl2" = "{ - .min_power = 25000, - .max_power = 64000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 1000,}" - - ## Charger Performance Control (Control, mA) - register "controls.charger_perf[0]" = "{ 255, 1700 }" - register "controls.charger_perf[1]" = "{ 24, 1500 }" - register "controls.charger_perf[2]" = "{ 16, 1000 }" - register "controls.charger_perf[3]" = "{ 8, 500 }" - - ## Fan Performance Control (Percent, Speed, Noise, Power) - register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" - register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" - register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" - register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" - register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" - register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" - register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" - register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" - register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" - register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" - - # Fan options - register "options.fan.fine_grained_control" = "1" - register "options.fan.step_size" = "2" - - device generic 0 on end - end - end # DPTF 0x1903 - device pci 14.0 on - chip drivers/usb/acpi - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Left"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 3)" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Right"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Right"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 2.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Middle"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Left"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 2.5 on end - end - chip drivers/usb/acpi - device usb 2.6 off end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Left"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Right"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Right"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 3)" - device usb 3.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Left"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 3.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Middle"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 3.5 on end - end - end - end - end # USB xHCI - device pci 15.0 off - # RFU - Reserved for Future Use. - end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 on - chip drivers/i2c/generic - register "hid" = ""1AF80175"" - register "name" = ""PS17"" - register "desc" = ""Parade PS175"" - device i2c 4a on end - end - end # I2C #2, PCON PS175. - device pci 15.3 on - chip drivers/i2c/generic - register "hid" = ""10EC2142"" - register "name" = ""RTD2"" - register "desc" = ""Realtek RTD2142"" - device i2c 4a on end - end - end # I2C #3, Realtek RTD2142. - device pci 16.0 on end # Management Engine Interface 1 - device pci 19.0 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" - register "property_count" = "1" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on end - end - end #I2C #4 - device pci 1a.0 on end # eMMC - device pci 1c.6 on - chip drivers/net - register "customized_leds" = "0x05af" - register "wake" = "GPE0_DW1_07" # GPP_C7 - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" - register "stop_delay_ms" = "12" # NIC needs time to quiesce - register "stop_off_delay_ms" = "1" - register "has_power_resource" = "1" - register "device_index" = "0" - device pci 00.0 on end - end - register "PcieRpSlotImplemented[6]" = "1" - end # RTL8111H Ethernet NIC - device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) - register "PcieRpSlotImplemented[10]" = "1" - end - device pci 1e.3 off end # GSPI #1 - end - - # VR Settings Configuration for 4 Domains - #+----------------+-------+-------+-------+-------+ - #| Domain/Setting | SA | IA | GTUS | GTS | - #+----------------+-------+-------+-------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | - #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | - #+----------------+-------+-------+-------+-------+ - #Note: IccMax settings are moved to SoC code - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 1004, - .dc_loadline = 1004, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 181, - .dc_loadline = 181, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 319, - .dc_loadline = 319, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 319, - .dc_loadline = 319, - }" - -end diff --git a/src/mainboard/google/hatch/variants/scout/Makefile.inc b/src/mainboard/google/hatch/variants/scout/Makefile.inc deleted file mode 100644 index 3b5b7d000d..0000000000 --- a/src/mainboard/google/hatch/variants/scout/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ramstage-y += gpio.c -bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/scout/gpio.c b/src/mainboard/google/hatch/variants/scout/gpio.c deleted file mode 100644 index 55154364ac..0000000000 --- a/src/mainboard/google/hatch/variants/scout/gpio.c +++ /dev/null @@ -1,179 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <commonlib/helpers.h> - -static const struct pad_config gpio_table[] = { - /* A16 : SD_OC_ODL */ - PAD_CFG_GPI(GPP_A16, NONE, DEEP), - /* A18 : LAN_PE_ISOLATE_ODL */ - PAD_CFG_GPO(GPP_A18, 1, DEEP), - /* A19 : Not connected */ - PAD_NC(GPP_A19, NONE), - /* A20 : Not connected */ - PAD_NC(GPP_A20, NONE), - /* A23 : M2_WLAN_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), - - /* B5 : LAN_CLKREQ_ODL */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), - /* B6 : M2_SSD_CLKREQ_ODL */ - PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), - /* B7 : M2_TPU0_CLKREQ_ODL */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), - /* B8 : CLK_PCIE_REQ3 (not connected) */ - PAD_NC(GPP_B8, NONE), - /* B9 : M2_TPU1_CLKREQ_ODL */ - PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), - /* B10 : M2_WLAN_CLKREQ_ODL */ - PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), - - /* C0 : SMBCLK */ - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), - /* C1 : SMBDATA */ - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - /* C3 : PCH_MBCLK1_R (i350) */ - PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), - /* C4 : PCH_MBDAT1_R (i350) */ - PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), - /* C6: M2_WLAN_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), - /* C7 : LAN_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), - /* C10 : PCH_PCON_RST_ODL */ - PAD_CFG_GPO(GPP_C10, 1, DEEP), - /* C11 : PCH_PCON1_PDB_ODL */ - PAD_CFG_GPO(GPP_C11, 1, DEEP), - /* C12 : PCH_RX_TSUM_UART_TX */ - PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), - /* C13 : PCH_RX_TSUM_UART_RX */ - PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), - /* C15 : WLAN_OFF_L */ - PAD_CFG_GPO(GPP_C15, 1, DEEP), - /* C16 : PCH_I2C_RFU_SDA (NC) */ - PAD_NC(GPP_C16, NONE), - /* C17 : PCH_I2C_RFU_SCL (NC) */ - PAD_NC(GPP_C17, NONE), - /* C18 : PCH_I2C_USI_SDA */ - PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), - /* C19 : PCH_I2C_USI_SDL */ - PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), - - /* D13 : SMBUS_ISP_SCALAR */ - PAD_CFG_GPO(GPP_D13, 0, DEEP), - /* D14 : EC_PCH_INT_L */ - PAD_CFG_GPI_APIC(GPP_D14, NONE, PLTRST, LEVEL, INVERT), - /* D15 : USI_RST_L */ - PAD_CFG_GPO(GPP_D15, 1, DEEP), - /* D16 TOUCH_INT */ - PAD_CFG_GPI_IRQ_WAKE(GPP_D16, NONE, PLTRST, LEVEL, INVERT), - - /* E2 : Not connected */ - PAD_NC(GPP_E2, NONE), - /* E3 : TPU_RST_PIN40 */ - PAD_CFG_GPO(GPP_E3, 1, DEEP), - /* E7 : TPU_RST_PIN42 */ - PAD_CFG_GPO(GPP_E7, 1, DEEP), - /* E9 : PU 10K to PP3300_SOC_A */ - PAD_NC(GPP_E9, NONE), - /* E10 : USB_A1_OC_ODL */ - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), - /* E15 : PCH_TYPEC_UPFB */ - PAD_CFG_GPI(GPP_E15, NONE, DEEP), - - /* E18 : DDI1_CLK */ - PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), - /* E19 : DDI1_DATA */ - PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), - - /* F11 : EMMC_CMD */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), - /* F12 : EMMC_DATA0 */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), - /* F13 : EMMC_DATA1 */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), - /* F14 : EMMC_DATA2 */ - PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), - /* F15 : EMMC_DATA3 */ - PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), - /* F16 : EMMC_DATA4 */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), - /* F17 : EMMC_DATA5 */ - PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), - /* F18 : EMMC_DATA6 */ - PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), - /* F19 : EMMC_DATA7 */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - /* F20 : EMMC_RCLK */ - PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), - /* F21 : EMMC_CLK */ - PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), - /* F22 : EMMC_RST_L */ - PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), - - /* H4: PCH_I2C_SCALER_SDA */ - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* H5: PCH_I2C_SCALER_SCL */ - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* H6 : PCH_I2C_TPU_SDA */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), - /* H7 : PCH_I2C_TPU_SCL */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), - /* H8 : NC */ - PAD_NC(GPP_H8, NONE), - /* H9 : NC */ - PAD_NC(GPP_H9, NONE), - /* H10 : NC */ - PAD_NC(GPP_H10, NONE), - /* H11 : NC */ - PAD_NC(GPP_H11, NONE), - /* H22 : PWM_PP3300_BIOZZER */ - PAD_CFG_GPO(GPP_H22, 0, DEEP), -}; - -const struct pad_config *override_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* B14 : GPP_B14_STRAP */ - PAD_NC(GPP_B14, NONE), - /* B22 : GPP_B22_STRAP */ - PAD_NC(GPP_B22, NONE), - /* E19 : GPP_E19_STRAP */ - PAD_NC(GPP_E19, NONE), - /* E21 : GPP_E21_STRAP */ - PAD_NC(GPP_E21, NONE), - /* B15 : H1_SLAVE_SPI_CS_L */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* B16 : H1_SLAVE_SPI_CLK */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* B17 : H1_SLAVE_SPI_MISO_R */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* B18 : H1_SLAVE_SPI_MOSI_R */ - PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* C14 : BT_DISABLE_L */ - PAD_CFG_GPO(GPP_C14, 0, DEEP), - /* PCH_WP_OD */ - PAD_CFG_GPI(GPP_C20, NONE, DEEP), - /* C21 : H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), - /* C22 : EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_C22, NONE, DEEP), - /* C23 : WLAN_PE_RST# */ - PAD_CFG_GPO(GPP_C23, 1, DEEP), - /* E1 : M2_SSD_PEDET */ - PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), - /* E5 : SATA_DEVSLP1 */ - PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), -}; - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} diff --git a/src/mainboard/google/hatch/variants/scout/include/variant/ec.h b/src/mainboard/google/hatch/variants/scout/include/variant/ec.h deleted file mode 100644 index 59fb3783c5..0000000000 --- a/src/mainboard/google/hatch/variants/scout/include/variant/ec.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_EC_H -#define VARIANT_EC_H - -#include <puff/ec.h> - -#endif diff --git a/src/mainboard/google/hatch/variants/scout/include/variant/gpio.h b/src/mainboard/google/hatch/variants/scout/include/variant/gpio.h deleted file mode 100644 index 9dd243400d..0000000000 --- a/src/mainboard/google/hatch/variants/scout/include/variant/gpio.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include <baseboard/gpio.h> - -#undef EC_SYNC_IRQ -#define EC_SYNC_IRQ GPP_D14_IRQ - -#endif diff --git a/src/mainboard/google/hatch/variants/scout/overridetree.cb b/src/mainboard/google/hatch/variants/scout/overridetree.cb deleted file mode 100644 index 8e6bc7714b..0000000000 --- a/src/mainboard/google/hatch/variants/scout/overridetree.cb +++ /dev/null @@ -1,514 +0,0 @@ -chip soc/intel/cannonlake - # Auto-switch between X4 NVMe and X2 NVMe. - register "TetonGlacierMode" = "1" - - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, - [PchSerialIoIndexSPI0] = PchSerialIoPci, - [PchSerialIoIndexSPI1] = PchSerialIoPci, - [PchSerialIoIndexSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoSkipInit, - [PchSerialIoIndexUART1] = PchSerialIoPci, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - - # USB configuration - register "usb2_ports[0]" = "{ - .enable = 1, - .ocpin = OC2, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_11P25MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 2 - register "usb2_ports[1]" = "{ - .enable = 1, - .ocpin = OC1, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 1 - register "usb2_ports[2]" = "{ - .enable = 1, - .ocpin = OC3, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 3 - register "usb2_ports[3]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-C Port - register "usb2_ports[4]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 4 - register "usb2_ports[5]" = "{ - .enable = 1, - .ocpin = OC0, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A port 0 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" - register "usb2_ports[9]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # BT - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 - - # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ - USB_PORT_WAKE_ENABLE(6)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ - USB_PORT_WAKE_ENABLE(6)" - - # Enable eMMC HS400 - register "ScsEmmcHs400Enabled" = "1" - - # EMMC Tx CMD Delay - # Refer to EDS-Vol2-14.3.7. - # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" - - # EMMC TX DATA Delay 1 - # Refer to EDS-Vol2-14.3.8. - # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. - # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" - - # EMMC TX DATA Delay 2 - # Refer to EDS-Vol2-14.3.9. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. - # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" - - # EMMC RX CMD/DATA Delay 1 - # Refer to EDS-Vol2-14.3.10. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. - # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" - - # EMMC RX CMD/DATA Delay 2 - # Refer to EDS-Vol2-14.3.12. - # [17:16] stands for Rx Clock before Output Buffer, - # 00: Rx clock after output buffer, - # 01: Rx clock before output buffer, - # 10: Automatic selection based on working mode. - # 11: Reserved - # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" - - # EMMC Rx Strobe Delay - # Refer to EDS-Vol2-14.3.11. - # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. - # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" - - # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. - register "PchHdaAudioLinkSsp1" = "0" - register "PchHdaAudioLinkDmic0" = "0" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| I2C1 | USI (Touch screen) | - #| I2C2 | SCALER | - #| I2C3 | TPU | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - }" - - # PCIe root port 7 for LAN - register "PcieRpEnable[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" - # Uses CLK SRC 0 - register "PcieClkSrcUsage[0]" = "6" - register "PcieClkSrcClkReq[0]" = "0" - - # PCIe root port 8 for WLAN - register "PcieRpEnable[7]" = "1" - register "PcieRpLtrEnable[7]" = "1" - # Uses CLK SRC 3 - register "PcieClkSrcUsage[3]" = "7" - register "PcieClkSrcClkReq[3]" = "3" - - # PCIe root port 9 for SSD (PCIe Lanes 9-12) - register "PcieRpEnable[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" - # RP 9 uses CLK SRC 1 - register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcClkReq[1]" = "1" - - # PCIe root port 10-12 disabled - register "PcieRpEnable[9]" = "0" - register "PcieRpEnable[10]" = "0" - register "PcieRpEnable[11]" = "0" - - # PCIe root port 13 TPU0 - register "PcieRpEnable[12]" = "1" - register "PcieRpLtrEnable[12]" = "1" - # RP 13 uses CLK SRC 2 - register "PcieClkSrcUsage[2]" = "12" - register "PcieClkSrcClkReq[2]" = "2" - - # PCIe root port 14 TPU1 - register "PcieRpEnable[13]" = "1" - register "PcieRpLtrEnable[13]" = "1" - # RP 14 uses CLK SRC 4 - register "PcieClkSrcUsage[4]" = "13" - register "PcieClkSrcClkReq[4]" = "4" - - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "vSD3_CD_B" - - # SATA port 1 Gen3 Strength - # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB - register "sata_port[1].TxGen3DeEmphEnable" = "1" - register "sata_port[1].TxGen3DeEmph" = "0x20" - - device domain 0 on - device pci 04.0 on - chip drivers/intel/dptf - ## Active Policy - register "policies.active[0]" = "{.target=DPTF_CPU, - .thresholds={TEMP_PCT(94, 0),}}" - register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, - .thresholds={TEMP_PCT(82, 80), - TEMP_PCT(80, 70), - TEMP_PCT(78, 60), - TEMP_PCT(75, 50), - TEMP_PCT(73, 40), - TEMP_PCT(35, 30),}}" - - ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 5000)" - register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 5000)" - - ## Critical Policy - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN)" - register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN)" - - ## Power Limits Control - # PL1 is fixed at 15W, avg over 28-32s interval - # 51-51W PL2 in 1000mW increments, avg over 28-32s interval - register "controls.power_limits.pl1" = "{ - .min_power = 15000, - .max_power = 15000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 125,}" - register "controls.power_limits.pl2" = "{ - .min_power = 51000, - .max_power = 51000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 1000,}" - - ## Charger Performance Control (Control, mA) - register "controls.charger_perf[0]" = "{ 255, 1700 }" - register "controls.charger_perf[1]" = "{ 24, 1500 }" - register "controls.charger_perf[2]" = "{ 16, 1000 }" - register "controls.charger_perf[3]" = "{ 8, 500 }" - - ## Fan Performance Control (Percent, Speed, Noise, Power) - register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" - register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" - register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" - register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" - register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" - register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" - register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" - register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" - register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" - register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" - - # Fan options - register "options.fan.fine_grained_control" = "1" - register "options.fan.step_size" = "2" - - device generic 0 on end - end - end # DPTF 0x1903 - device pci 14.0 on - chip drivers/usb/acpi - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Left"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 3)" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Right"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Right"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 2.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Middle"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Left"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 2.5 on end - end - chip drivers/usb/acpi - device usb 2.6 off end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Left"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Right"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Right"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 3)" - device usb 3.3 on end - end - chip drivers/usb/acpi - # USB3 Port 5 is not populated - device usb 3.4 off end - end - chip drivers/usb/acpi - register "desc" = ""USB3 M.2 HDMI-to-USB"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(2, 0)" - device usb 3.5 on end - end - end - end - end # USB xHCI - device pci 15.0 off - # RFU - Reserved for Future Use. - end # I2C #0 - device pci 15.1 on # I2C #1, USI (Touch screen) - chip drivers/i2c/hid - register "generic.hid" = ""ILTK0001"" - register "generic.desc" = ""ILITEK Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "600" - register "generic.wake" = "GPE0_DW2_16" - register "generic.has_power_resource" = "1" - register "generic.disable_gpio_export_in_crs" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 41 on end - end - end - device pci 15.2 on end # I2C #2, SCALER - device pci 15.3 on end # I2C #3, TPU - device pci 16.0 on end # Management Engine Interface 1 - device pci 19.0 off end # I2C #4 - device pci 1a.0 on end # eMMC - device pci 1c.6 on # PCI Root Port 7 (LAN) - chip drivers/net # RTL8111H Ethernet NIC - register "customized_leds" = "0x05af" - register "wake" = "GPE0_DW1_07" # GPP_C7 - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" - register "stop_delay_ms" = "12" # NIC needs time to quiesce - register "stop_off_delay_ms" = "1" - register "has_power_resource" = "1" - register "device_index" = "0" - device pci 00.0 on end - end - end - device pci 1c.7 on # PCI Root Port 8 (WLAN) - register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot - end - device pci 1d.0 on # PCI Root Port 9 (SSD) - register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot - end - device pci 1d.1 off end # PCI Root Port 10 (Not connected) - device pci 1d.2 off end # PCI Root Port 11 (Not connected) - device pci 1d.3 off end # PCI Root Port 12 (Not connected) - device pci 1d.4 on # PCI Root Port 13 (TPU0) - register "PcieRpSlotImplemented[12]" = "1" # M.2 Slot - end - device pci 1d.5 on # PCI Root Port 14 (TPU1) - register "PcieRpSlotImplemented[13]" = "1" # M.2 Slot - end - device pci 1d.6 on end # PCI Root Port 15 (non-root) - device pci 1d.7 on end # PCI Root Port 16 (non-root) - device pci 1e.0 on end # UART #0 - device pci 1e.1 on end # UART #1 - device pci 1e.3 off end # GSPI #1 - end - - # VR Settings Configuration for 4 Domains - #+----------------+-------+-------+-------+-------+ - #| Domain/Setting | SA | IA | GTUS | GTS | - #+----------------+-------+-------+-------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | - #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | - #+----------------+-------+-------+-------+-------+ - #Note: IccMax settings are moved to SoC code - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 1004, - .dc_loadline = 1004, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 181, - .dc_loadline = 181, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 319, - .dc_loadline = 319, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 319, - .dc_loadline = 319, - }" - -end diff --git a/src/mainboard/google/hatch/variants/wyvern/Makefile.inc b/src/mainboard/google/hatch/variants/wyvern/Makefile.inc deleted file mode 100644 index 3b5b7d000d..0000000000 --- a/src/mainboard/google/hatch/variants/wyvern/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ramstage-y += gpio.c -bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/wyvern/data.vbt b/src/mainboard/google/hatch/variants/wyvern/data.vbt Binary files differdeleted file mode 100644 index cda1c25d7d..0000000000 --- a/src/mainboard/google/hatch/variants/wyvern/data.vbt +++ /dev/null diff --git a/src/mainboard/google/hatch/variants/wyvern/gpio.c b/src/mainboard/google/hatch/variants/wyvern/gpio.c deleted file mode 100644 index 996edc4fc7..0000000000 --- a/src/mainboard/google/hatch/variants/wyvern/gpio.c +++ /dev/null @@ -1,117 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <commonlib/helpers.h> - -static const struct pad_config gpio_table[] = { - /* A16 : SD_OC_ODL */ - PAD_CFG_GPI(GPP_A16, NONE, DEEP), - /* A18 : LAN_PE_ISOLATE_ODL */ - PAD_CFG_GPO(GPP_A18, 1, DEEP), - /* A23 : M2_WLAN_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), - - /* B5 : LAN_CLKREQ_ODL */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), - - /* C0 : SMBCLK */ - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), - /* C1 : SMBDATA */ - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - /* C6: M2_WLAN_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), - /* C7 : LAN_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), - /* C10 : PCH_PCON_RST_ODL */ - PAD_CFG_GPO(GPP_C10, 1, DEEP), - /* C11 : PCH_PCON_PDB_ODL */ - PAD_CFG_GPO(GPP_C11, 1, DEEP), - /* C15 : WLAN_OFF_L */ - PAD_CFG_GPO(GPP_C15, 1, DEEP), - - /* E2 : EN_PP_MST_OD */ - PAD_CFG_GPO(GPP_E2, 1, DEEP), - /* E9 : USB_A0_OC_ODL */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - /* E10 : USB_A1_OC_ODL */ - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), - - /* F11 : EMMC_CMD */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), - /* F12 : EMMC_DATA0 */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), - /* F13 : EMMC_DATA1 */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), - /* F14 : EMMC_DATA2 */ - PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), - /* F15 : EMMC_DATA3 */ - PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), - /* F16 : EMMC_DATA4 */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), - /* F17 : EMMC_DATA5 */ - PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), - /* F18 : EMMC_DATA6 */ - PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), - /* F19 : EMMC_DATA7 */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - /* F20 : EMMC_RCLK */ - PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), - /* F21 : EMMC_CLK */ - PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), - /* F22 : EMMC_RST_L */ - PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), - - /* H4: PCH_I2C_PCON_SDA */ - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* H5: PCH_I2C_PCON_SCL */ - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* H22 : PWM_PP3300_BIOZZER */ - PAD_CFG_GPO(GPP_H22, 0, DEEP), -}; - -const struct pad_config *override_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* B14 : GPP_B14_STRAP */ - PAD_NC(GPP_B14, NONE), - /* B22 : GPP_B22_STRAP */ - PAD_NC(GPP_B22, NONE), - /* E19 : GPP_E19_STRAP */ - PAD_NC(GPP_E19, NONE), - /* E21 : GPP_E21_STRAP */ - PAD_NC(GPP_E21, NONE), - /* B15 : H1_SLAVE_SPI_CS_L */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* B16 : H1_SLAVE_SPI_CLK */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* B17 : H1_SLAVE_SPI_MISO_R */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* B18 : H1_SLAVE_SPI_MOSI_R */ - PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* C14 : BT_DISABLE_L */ - PAD_CFG_GPO(GPP_C14, 0, DEEP), - /* PCH_WP_OD */ - PAD_CFG_GPI(GPP_C20, NONE, DEEP), - /* C21 : H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), - /* C22 : EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_C22, NONE, DEEP), - /* C23 : WLAN_PE_RST# */ - PAD_CFG_GPO(GPP_C23, 1, DEEP), - /* E1 : M2_SSD_PEDET */ - PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), - /* E5 : SATA_DEVSLP1 */ - PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), -}; - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} diff --git a/src/mainboard/google/hatch/variants/wyvern/include/variant/ec.h b/src/mainboard/google/hatch/variants/wyvern/include/variant/ec.h deleted file mode 100644 index 59fb3783c5..0000000000 --- a/src/mainboard/google/hatch/variants/wyvern/include/variant/ec.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_EC_H -#define VARIANT_EC_H - -#include <puff/ec.h> - -#endif diff --git a/src/mainboard/google/hatch/variants/wyvern/include/variant/gpio.h b/src/mainboard/google/hatch/variants/wyvern/include/variant/gpio.h deleted file mode 100644 index 79a141008f..0000000000 --- a/src/mainboard/google/hatch/variants/wyvern/include/variant/gpio.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include <baseboard/gpio.h> - -#endif diff --git a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb deleted file mode 100644 index b9dd489cf2..0000000000 --- a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb +++ /dev/null @@ -1,483 +0,0 @@ -chip soc/intel/cannonlake - - # Auto-switch between X4 NVMe and X2 NVMe. - register "TetonGlacierMode" = "1" - - register "SataPortsEnable[0]" = "1" - - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - [PchSerialIoIndexSPI0] = PchSerialIoPci, - [PchSerialIoIndexSPI1] = PchSerialIoPci, - [PchSerialIoIndexSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoSkipInit, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - - # No need for dynamic config (and the additional RAM training time) - # on a Chromebox; always use high power/high performance mode - register "SaGv" = "SaGv_FixedHigh" - - # USB configuration - register "usb2_ports[0]" = "{ - .enable = 1, - .ocpin = OC2, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_11P25MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 2 - register "usb2_ports[1]" = "{ - .enable = 1, - .ocpin = OC1, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 1 - register "usb2_ports[2]" = "{ - .enable = 1, - .ocpin = OC3, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 3 - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port - register "usb2_ports[4]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 4 - register "usb2_ports[5]" = "{ - .enable = 1, - .ocpin = OC0, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A port 0 - register "usb2_ports[9]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # BT - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 - - # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(6)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5)" - - # Enable eMMC HS400 - register "ScsEmmcHs400Enabled" = "1" - - # EMMC Tx CMD Delay - # Refer to EDS-Vol2-14.3.7. - # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" - - # EMMC TX DATA Delay 1 - # Refer to EDS-Vol2-14.3.8. - # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. - # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" - - # EMMC TX DATA Delay 2 - # Refer to EDS-Vol2-14.3.9. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. - # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" - - # EMMC RX CMD/DATA Delay 1 - # Refer to EDS-Vol2-14.3.10. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. - # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" - - # EMMC RX CMD/DATA Delay 2 - # Refer to EDS-Vol2-14.3.12. - # [17:16] stands for Rx Clock before Output Buffer, - # 00: Rx clock after output buffer, - # 01: Rx clock before output buffer, - # 10: Automatic selection based on working mode. - # 11: Reserved - # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" - - # EMMC Rx Strobe Delay - # Refer to EDS-Vol2-14.3.11. - # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. - # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" - - # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. - register "PchHdaAudioLinkSsp1" = "0" - register "PchHdaAudioLinkDmic0" = "0" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| I2C0 | RFU | - #| I2C2 | PS175 | - #| I2C3 | MST | - #| I2C4 | Audio | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 0, - .fall_time_ns = 0, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - .i2c[4] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 60, - .fall_time_ns = 60, - }, - }" - - # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" - # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" - # Uses CLK SRC 0 - register "PcieClkSrcUsage[0]" = "6" - register "PcieClkSrcClkReq[0]" = "0" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "vSD3_CD_B" - - # SATA port 1 Gen3 Strength - # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB - register "sata_port[1].TxGen3DeEmphEnable" = "1" - register "sata_port[1].TxGen3DeEmph" = "0x20" - - device domain 0 on - device pci 04.0 on - chip drivers/intel/dptf - ## Active Policy - register "policies.active[0]" = "{.target=DPTF_CPU, - .thresholds={TEMP_PCT(90, 85), - TEMP_PCT(85, 75), - TEMP_PCT(80, 65), - TEMP_PCT(75, 55), - TEMP_PCT(70, 45),}}" - register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, - .thresholds={TEMP_PCT(50, 85), - TEMP_PCT(47, 75), - TEMP_PCT(45, 65), - TEMP_PCT(42, 55), - TEMP_PCT(39, 45),}}" - - ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" - - ## Critical Policy - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" - - ## Power Limits Control - # PL1 is fixed at 15W, avg over 28-32s interval - # 25-64W PL2 in 1000mW increments, avg over 28-32s interval - register "controls.power_limits.pl1" = "{ - .min_power = 15000, - .max_power = 15000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200,}" - register "controls.power_limits.pl2" = "{ - .min_power = 25000, - .max_power = 64000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 1000,}" - - ## Charger Performance Control (Control, mA) - register "controls.charger_perf[0]" = "{ 255, 1700 }" - register "controls.charger_perf[1]" = "{ 24, 1500 }" - register "controls.charger_perf[2]" = "{ 16, 1000 }" - register "controls.charger_perf[3]" = "{ 8, 500 }" - - ## Fan Performance Control (Percent, Speed, Noise, Power) - register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" - register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" - register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" - register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" - register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" - register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" - register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" - register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" - register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" - register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" - - # Fan options - register "options.fan.fine_grained_control" = "1" - register "options.fan.step_size" = "2" - - device generic 0 on end - end - end # DPTF 0x1903 - device pci 14.0 on - chip drivers/usb/acpi - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Left"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 3)" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Right"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Right"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 2.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Middle"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Left"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 2.5 on end - end - chip drivers/usb/acpi - device usb 2.6 off end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Left"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Right"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Right"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 3)" - device usb 3.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Left"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 3.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Middle"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 3.5 on end - end - end - end - end # USB xHCI - device pci 15.0 off - # RFU - Reserved for Future Use. - end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 on - chip drivers/i2c/generic - register "hid" = ""1AF80175"" - register "name" = ""PS17"" - register "desc" = ""Parade PS175"" - device i2c 4a on end - end - end # I2C #2, PCON PS175. - device pci 15.3 on - chip drivers/i2c/generic - register "hid" = ""10EC2142"" - register "name" = ""RTD2"" - register "desc" = ""Realtek RTD2142"" - device i2c 4a on end - end - end # I2C #3, Realtek RTD2142. - device pci 16.0 on end # Management Engine Interface 1 - device pci 19.0 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" - register "property_count" = "1" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on end - end - end #I2C #4 - device pci 1a.0 on end # eMMC - device pci 1c.6 on - chip drivers/net - register "customized_leds" = "0x05af" - register "wake" = "GPE0_DW1_07" # GPP_C7 - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" - register "stop_delay_ms" = "12" # NIC needs time to quiesce - register "stop_off_delay_ms" = "1" - register "has_power_resource" = "1" - register "device_index" = "0" - device pci 00.0 on end - end - register "PcieRpSlotImplemented[6]" = "1" - end # RTL8111H Ethernet NIC - device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) - register "PcieRpSlotImplemented[10]" = "1" - end - device pci 1e.3 off end # GSPI #1 - end - - # VR Settings Configuration for 4 Domains - #+----------------+-------+-------+-------+-------+ - #| Domain/Setting | SA | IA | GTUS | GTS | - #+----------------+-------+-------+-------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | - #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | - #+----------------+-------+-------+-------+-------+ - #Note: IccMax settings are moved to SoC code - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 1004, - .dc_loadline = 1004, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 181, - .dc_loadline = 181, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 319, - .dc_loadline = 319, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = 0, - .voltage_limit = 1520, - .ac_loadline = 319, - .dc_loadline = 319, - }" - -end |