summaryrefslogtreecommitdiff
path: root/src/mainboard/google/hatch
diff options
context:
space:
mode:
authorPatrick Rudolph <patrick.rudolph@9elements.com>2020-11-30 15:50:06 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-02-04 10:21:42 +0000
commit31218a4259708233c17fa8b09fa9d9c06ea1f2ad (patch)
treea1d32df5213f557c61430bc341da1b64aa7f7c4d /src/mainboard/google/hatch
parent37cae540343d8f02258c3209f90114e7189753e2 (diff)
drivers/intel/fsp2_0: Fix running on x86_64
Add new Kconfig symbols to mark FSP binary as x86_32. Fix the FSP headers and replace void pointers by fixed sized integers depending on the used mode to compile the FSP. This issue has been reported here: https://github.com/intel/FSP/issues/59 This is necessary to run on x86_64, as pointers have different size. Add preprocessor error to warn that x86_64 FSP isn't supported by the current code. Tested on Intel Skylake. FSP-M no longer returns the error "Invalid Parameter". Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/google/hatch')
-rw-r--r--src/mainboard/google/hatch/romstage_spd_smbus.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c
index e697379965..3d84e52448 100644
--- a/src/mainboard/google/hatch/romstage_spd_smbus.c
+++ b/src/mainboard/google/hatch/romstage_spd_smbus.c
@@ -28,10 +28,10 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
printk(BIOS_WARNING, "Invalid SPD cache\n");
} else {
dimm_changed = check_if_dimm_changed(spd_cache, &blk);
- if (dimm_changed && memupd->FspmArchUpd.NvsBufferPtr != NULL) {
+ if (dimm_changed && memupd->FspmArchUpd.NvsBufferPtr != 0) {
/* Set mrc_cache as invalid */
printk(BIOS_INFO, "Set mrc_cache as invalid\n");
- memupd->FspmArchUpd.NvsBufferPtr = NULL;
+ memupd->FspmArchUpd.NvsBufferPtr = 0;
}
}
need_update_cache = true;