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authorFurquan Shaikh <furquan@google.com>2019-06-01 14:44:56 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-06-04 11:20:42 +0000
commitfca7c4d614eeee1b040cfeba37599b32d0ad55f1 (patch)
treeaf017cdc1552f05e57026ed604b4aadfd2b92ba0 /src/mainboard/google/hatch/variants
parenta99ed13e3397bc536012120aab8cadb827913863 (diff)
mb/google/hatch: Enable LTR for PCIe ports
Enable LTR for NVMe and WiFi PCIe ports so that they can use ASPM L1.2 BUG=b:134195632 TEST=Verified L1 substate with lspci on hatch: Before: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+ After: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ Change-Id: I7fce60897b78dde12747ac7fb857c988d16118ab Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33161 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/hatch/variants')
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/devicetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 9d10cac41b..1123d53734 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -72,6 +72,7 @@ chip soc/intel/cannonlake
# Enable Root port 9(x4) for NVMe.
register "PcieRpEnable[8]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
# RP 9 uses CLK SRC 1
register "PcieClkSrcUsage[1]" = "8"
# ClkReq-to-ClkSrc mapping for CLK SRC 1
@@ -79,6 +80,7 @@ chip soc/intel/cannonlake
# PCIe port 14 for M.2 E-key WLAN
register "PcieRpEnable[13]" = "1"
+ register "PcieRpLtrEnable[13]" = "1"
# RP 14 uses CLK SRC 3
register "PcieClkSrcUsage[3]" = "13"
register "PcieClkSrcClkReq[3]" = "3"