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authorMario Scheithauer <mario.scheithauer@siemens.com>2021-11-12 11:28:15 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-11-15 11:19:50 +0000
commit436eac827aea4839169f2421006df42b8c5c379f (patch)
tree285ac152c1dc60de53adce4d1a67e96d2d6fc20d /src/mainboard/google/hatch/variants/wyvern/gpio.c
parented784bc0a79ce1c296a2685f22cb269d510403dd (diff)
mb/siemens/mc_ehl2: Adjust PCIe clock source settings in devicetree
With latest hardware revision all clock outputs will be used on this mainboard. For this reason set all clock source mappings to 'PCIE_CLK_FREE' to have a free running clock. Change-Id: Ic3f6fb4e24128742ed72dade7a4555c39fb722ae Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/google/hatch/variants/wyvern/gpio.c')
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