summaryrefslogtreecommitdiff
path: root/src/mainboard/google/hatch/variants/mushu
diff options
context:
space:
mode:
authorEdward O'Callaghan <quasisec@google.com>2019-12-24 14:11:43 +1100
committerEdward O'Callaghan <quasisec@chromium.org>2019-12-25 07:04:02 +0000
commitc4a3f51618a7575628fb513133952ac57326fc24 (patch)
tree1e496762347ba1f0dab5e454ddfd9aa030c32e58 /src/mainboard/google/hatch/variants/mushu
parent60889e55ea0076f442833e0bfc94fe828bb5d4b3 (diff)
mainboard/google/hatch: Move gpio GPP_A* NC down into baseboard
The baseboard GPIO table definitions are too straineous to the extend that variants need to redefine assumptions back to NC. Invert this so that baseboard by default assumes the safer NC and move the specific board configurations to their respective places. This patch handles the GPP_A* group for easier review. BUG=b:142094759 BRANCH=none TEST=builds Change-Id: I29b4323ac80b1288b2562846217c4f377714fc2c Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/hatch/variants/mushu')
-rw-r--r--src/mainboard/google/hatch/variants/mushu/gpio.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c
index 56f587b6b8..a2adf25371 100644
--- a/src/mainboard/google/hatch/variants/mushu/gpio.c
+++ b/src/mainboard/google/hatch/variants/mushu/gpio.c
@@ -19,6 +19,18 @@
#include <commonlib/helpers.h>
static const struct pad_config gpio_table[] = {
+ /* A0 : SAR0_INT_ODL */
+ PAD_CFG_GPI_INT(GPP_A0, NONE, PLTRST, LEVEL),
+ /* A6 : SAR1_INT_ODL */
+ PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL),
+ /* A8 : PEN_GARAGE_DET_L (wake) */
+ PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE),
+ /* A10 : FPMCU_PCH_BOOT1 */
+ PAD_CFG_GPO(GPP_A10, 0, DEEP),
+ /* A11 : PCH_SPI_FPMCU_CS_L */
+ PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2),
+ /* A12 : FPMCU_RST_ODL */
+ PAD_CFG_GPO(GPP_A12, 0, DEEP),
/* C13 : EC_PCH_INT_L */
PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT)};