diff options
| author | Seunghwan Kim <sh_.kim@samsung.com> | 2019-07-18 15:51:31 +0900 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2019-07-31 20:51:32 +0000 |
| commit | d93ee950b355fa2b7665421c152101a6b5dc39a2 (patch) | |
| tree | 7b49620ab8a7d670e1a2eeed9ed5ef420096b9ad /src/mainboard/google/hatch/variants/kohaku/overridetree.cb | |
| parent | c3244ccca7b05f8b6f9b0ca996bd962fe5dd6b82 (diff) | |
mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2
Applying first tuned DPTF parameters and TDP PL1/PL2 values for kohaku.
More fine-tuning will happen later.
BUG=b:1704071
BRANCH=none
TEST=build
Change-Id: I8a87ff88e8e14ada473f9da59c15cdc779cbb108
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34397
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/hatch/variants/kohaku/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/hatch/variants/kohaku/overridetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index e463b8b3f6..fa64d60483 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -1,4 +1,7 @@ chip soc/intel/cannonlake + register "tdp_pl1_override" = "8" + register "tdp_pl2_override" = "51" + register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, |