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authorEdward O'Callaghan <quasisec@google.com>2019-12-24 15:35:44 +1100
committerEdward O'Callaghan <quasisec@chromium.org>2019-12-25 07:24:17 +0000
commitc735a31861d4d2fba4060184ef136b77166158b3 (patch)
tree34f914bfc523da440e245843cd2d721cc9c93f67 /src/mainboard/google/hatch/variants/kindred
parent3dbe593906d22ddcd113cad9065b38115d0163a6 (diff)
mainboard/google/hatch: Move gpio GPP_H3 config up from baseboard
The baseboard GPIO table definitions are too straineous to the extend that variants need to redefine assumptions back to NC. Invert this so that baseboard by default assumes the safer NC and move the specific board configurations to their respective places. This patch handles the GPP_H3 gpio config for easier review. This toggles the MAX amp which not all boards have. Move the pin configuration to boards with the respective devicetree configuration following on from the theme of commit b417786525. BUG=b:142094759 BRANCH=none TEST=builds Change-Id: Iefd2223af79a13c8a42d07bc10b2772dbff6d3e5 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/hatch/variants/kindred')
-rw-r--r--src/mainboard/google/hatch/variants/kindred/gpio.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c
index 19956b4f1e..fbb47f95de 100644
--- a/src/mainboard/google/hatch/variants/kindred/gpio.c
+++ b/src/mainboard/google/hatch/variants/kindred/gpio.c
@@ -65,6 +65,8 @@ static const struct pad_config ssd_sku_gpio_table[] = {
PAD_NC(GPP_F21, NONE),
/* F22 : EMMC_RESET# ==> NC */
PAD_NC(GPP_F22, NONE),
+ /* H3 : SPKR_PA_EN */
+ PAD_CFG_GPO(GPP_H3, 0, DEEP),
/* H19 : MEM_STRAP_0 */
PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
/* H22 : MEM_STRAP_1 */
@@ -124,6 +126,8 @@ static const struct pad_config emmc_sku_gpio_table[] = {
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
/* F22 : EMMC_RESET# ==> EMMC_RST_L */
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+ /* H3 : SPKR_PA_EN */
+ PAD_CFG_GPO(GPP_H3, 0, DEEP),
/* H19 : MEM_STRAP_0 */
PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
/* H22 : MEM_STRAP_1 */
@@ -177,6 +181,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
/* F22 : EMMC_RESET# ==> EMMC_RST_L */
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+ /* H3 : SPKR_PA_EN */
+ PAD_CFG_GPO(GPP_H3, 0, DEEP),
/* H19 : MEM_STRAP_0 */
PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
/* H22 : MEM_STRAP_1 */