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authorSumeet R Pawnikar <sumeet.r.pawnikar@intel.com>2020-05-09 16:37:30 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-05-26 15:02:54 +0000
commit309ccf74dd7c25874572c6a62ffc7042dcdadc66 (patch)
tree7b1e79798c0607ef794bb4cd24c575713a552db5 /src/mainboard/google/hatch/variants/helios_diskswap
parent7d054bd38f5cfe36f6abd4f4422c463243bc3749 (diff)
cannonlake: update processor power limits configuration
Update processor power limit configuration parameters based on common code base support for Intel Cannonlake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on drallion system Change-Id: Iac6e6f81343fcd769619e9d7ac339430966834f6 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/hatch/variants/helios_diskswap')
-rw-r--r--src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb
index 8a3745d174..0422a57bd3 100644
--- a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb
@@ -1,6 +1,8 @@
chip soc/intel/cannonlake
- register "tdp_pl1_override" = "13"
- register "tdp_pl2_override" = "64"
+ register "power_limits_config" = "{
+ .tdp_pl1_override = 13,
+ .tdp_pl2_override = 64,
+ }"
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,