diff options
| author | Edward O'Callaghan <quasisec@google.com> | 2019-12-24 15:35:44 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2019-12-25 07:24:17 +0000 |
| commit | c735a31861d4d2fba4060184ef136b77166158b3 (patch) | |
| tree | 34f914bfc523da440e245843cd2d721cc9c93f67 /src/mainboard/google/hatch/variants/baseboard | |
| parent | 3dbe593906d22ddcd113cad9065b38115d0163a6 (diff) | |
mainboard/google/hatch: Move gpio GPP_H3 config up from baseboard
The baseboard GPIO table definitions are too straineous to the extend
that variants need to redefine assumptions back to NC. Invert this so
that baseboard by default assumes the safer NC and move the specific
board configurations to their respective places.
This patch handles the GPP_H3 gpio config for easier review. This
toggles the MAX amp which not all boards have. Move the pin
configuration to boards with the respective devicetree configuration
following on from the theme of commit b417786525.
BUG=b:142094759
BRANCH=none
TEST=builds
Change-Id: Iefd2223af79a13c8a42d07bc10b2772dbff6d3e5
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/hatch/variants/baseboard')
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/gpio.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 2c3bf8d546..dcd987fbb4 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -334,8 +334,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* H2 : CNV_CLKREQ0 */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), - /* H3 : SPKR_PA_EN */ - PAD_CFG_GPO(GPP_H3, 0, DEEP), + /* H3 : GPP_H3 ==> NC */ + PAD_NC(GPP_H3, NONE), /* H4 : PCH_I2C_PEN_SDA */ PAD_NC(GPP_H4, NONE), /* H5 : PCH_I2C_PEN_SCL */ |