diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2019-09-10 08:51:02 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2019-09-12 06:20:10 +0000 |
| commit | 8dda419b3cb55b47970ed3dcd9f942910ace43ff (patch) | |
| tree | e98c6d3e32a0b8c35ac549c061a1202180586c68 /src/mainboard/google/hatch/variants/baseboard | |
| parent | 87bb5f5e7a4476a2e9a70cc8d234fa0b479f1e26 (diff) | |
mb/google/hatch: Configure SATA DEVSLP pad reset config to PLT_RST
BUG=b:133000685
Change-Id: Ia12174e3254153dbca55070f5daf84fd8aac51d0
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Diffstat (limited to 'src/mainboard/google/hatch/variants/baseboard')
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 8b5fc1a403..7382209264 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -24,6 +24,8 @@ chip soc/intel/cannonlake register "SataMode" = "Sata_AHCI" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" + # Configure devslp pad reset to PLT_RST + register "SataPortsDevSlpResetConfig[1]" = "SataDevSlpPlatformReset" register "satapwroptimize" = "1" # Enable System Agent dynamic frequency register "SaGv" = "SaGv_Enabled" |