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authorFurquan Shaikh <furquan@google.com>2019-04-10 10:26:12 -0700
committerFurquan Shaikh <furquan@google.com>2019-04-12 02:15:32 +0000
commit29368167b58689622a77c41cfa0aab14bd72f0ec (patch)
treee5cbc92e0887eaa852d6b7689aaaed0035b7e774 /src/mainboard/google/hatch/variants/baseboard
parentaea9871a62173264fd4878486c49df5f5d4f8cfc (diff)
mb/google/hatch: Use GPIO IRQ for sx9310 device
This change uses GPIO IRQ instead of IOAPIC for GPP_A0 pad which is the interrupt line for sx9310. This is required because IRQ# used by GPP_A0 is allocated for PIRQ which does not allow IRQ# sharing. Additionally, this change also configures GPP_A6 for GPIO IRQ. GPP_A6 is currently unused in the devicetree. BUG=b:129794308 TEST=Verified that there are no interrupt storms on GPP_A0. Change-Id: Ibb510a647391c0d9cb854d23656bb4b1cb7756ab Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard/google/hatch/variants/baseboard')
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/gpio.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c
index 1c8cfba759..eaa8dd343a 100644
--- a/src/mainboard/google/hatch/variants/baseboard/gpio.c
+++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c
@@ -20,14 +20,14 @@
static const struct pad_config gpio_table[] = {
/* A0 : SAR0_INT_ODL */
- PAD_CFG_GPI_APIC(GPP_A0, NONE, PLTRST, LEVEL, NONE),
+ PAD_CFG_GPI_INT(GPP_A0, NONE, PLTRST, LEVEL),
/* A1 : ESPI_IO0 */
/* A2 : ESPI_IO1 */
/* A3 : ESPI_IO2 */
/* A4 : ESPI_IO3 */
/* A5 : ESPI_CS# */
/* A6 : SAR1_INT_ODL */
- PAD_CFG_GPI_APIC(GPP_A6, NONE, PLTRST, LEVEL, NONE),
+ PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL),
/* A7 : PP3300_SOC_A */
PAD_NC(GPP_A7, NONE),
/* A8 : EMR_GARAGE_DET */