soc/intel/cannonlake: Support different SPD read type for each slot

Also clean up cannonlake_memcfg_init.

The major changes include:
(1) Add enum 'mem_info_read_type' to spd_info.
(2) Add per-dimm-slot spd_info to cnl_mb_cfg.
(3) Setup memory config for each slot independently.
(4) Squash meminit_memcfg_spd().

BUG=chromium:960581, b:124990009
BRANCH=none
TEST=boot hatch, hatch_whl, and kohaku

Change-Id: I686a85996858204c20fd05ef24787a0487817c34
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32513
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 2 insertions, 41 deletions

diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
index 5d6311ba24..e83732cb62 100644
--- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
@@ -22,13 +22,6 @@
 
 #define GPIO_PCH_WP	        GPP_C20
 
-/* Memory configuration board straps */
-#define GPIO_MEM_CONFIG_0	GPP_F20
-#define GPIO_MEM_CONFIG_1	GPP_F21
-#define GPIO_MEM_CONFIG_2	GPP_F11
-#define GPIO_MEM_CONFIG_3	GPP_F22
-
-
 /* EC wake pin is LAN_WAKE# */
 #define GPE_EC_WAKE		GPE0_LAN_WAK
 
diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
index d41ad536f2..17bd5df63d 100644
--- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
@@ -31,9 +31,6 @@ const struct pad_config *base_early_gpio_table(size_t *num);
 const struct pad_config *override_gpio_table(size_t *num);
 const struct pad_config *override_early_gpio_table(size_t *num);
 
-/* Return memory SKU for the board. */
-int variant_memory_sku(void);
-
 /* Return board specific memory configuration */
 void variant_memory_params(struct cnl_mb_cfg *bcfg);
 
diff --git a/src/mainboard/google/hatch/variants/baseboard/memory.c b/src/mainboard/google/hatch/variants/baseboard/memory.c
index 580bdc9ab3..bcfc49f20e 100644
--- a/src/mainboard/google/hatch/variants/baseboard/memory.c
+++ b/src/mainboard/google/hatch/variants/baseboard/memory.c
@@ -15,16 +15,15 @@
 
 #include <baseboard/variants.h>
 #include <baseboard/gpio.h>
-#include <gpio.h>
 #include <soc/cnl_memcfg_init.h>
 #include <string.h>
 
 static const struct cnl_mb_cfg baseboard_memcfg = {
 	/* Baseboard uses 121, 81 and 100 rcomp resistors */
-	.rcomp_resistor = { 121, 81, 100 },
+	.rcomp_resistor = {121, 81, 100},
 
 	/* Baseboard Rcomp target values */
-	.rcomp_targets = { 100, 40, 20, 20, 26 },
+	.rcomp_targets = {100, 40, 20, 20, 26},
 
 	/* Set CaVref config to 2 */
 	.vref_ca_config = 2,
@@ -36,32 +35,4 @@ static const struct cnl_mb_cfg baseboard_memcfg = {
 void __weak variant_memory_params(struct cnl_mb_cfg *bcfg)
 {
 	memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg));
-	/*
-	 * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single
-	 * channel skus and 0 for dual channel skus.
-	 */
-	if (gpio_get(GPP_F2) == 1) {
-		/*
-		 * Single channel config: for Hatch, Channel 0 is
-		 * always populated.
-		 */
-		bcfg->channel_empty[0] = 0;
-		bcfg->channel_empty[1] = 1;
-	} else {
-		/* Dual channel config: both channels populated. */
-		bcfg->channel_empty[0] = 0;
-		bcfg->channel_empty[1] = 0;
-	}
-}
-
-int __weak variant_memory_sku(void)
-{
-	const gpio_t spd_gpios[] = {
-		GPIO_MEM_CONFIG_0,
-		GPIO_MEM_CONFIG_1,
-		GPIO_MEM_CONFIG_2,
-		GPIO_MEM_CONFIG_3,
-	};
-
-	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
 }