diff options
| author | Shelley Chen <shchen@google.com> | 2019-01-25 14:44:42 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2019-01-30 06:32:23 +0000 |
| commit | fced3fe170c698231a35b83e4b13538ef08981a8 (patch) | |
| tree | ee9206268b6a029b3df7692aada484776059302d /src/mainboard/google/hatch/variants/baseboard/devicetree.cb | |
| parent | e81f334c5948f508bd91431e51f26249257e8c15 (diff) | |
mb/google/hatch: Enable AP Wake from EC
Initialize EC_PCH_WAKE_ODL GPIO to make sure that ec events will wake
the AP from suspend. Also create a task to initialize the hostevent
wake mask properly.
BUG=b:123325238,b:123325720
BRANCH=None
TEST=from AP console: powerd_dbus_suspend
from EC console: hostevent (make sure wake mask set)
from EC console: gpioset PCH_WAKE_L 0
Make sure device wakes up
Also, checked to make sure keyboard press wakes up
device from S3.
Change-Id: I53d5291a6b9ab9a21e89ccd21f172180ce473bd5
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/hatch/variants/baseboard/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 30a282b4b9..cea64e4237 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -250,7 +250,11 @@ chip soc/intel/cannonlake end end # GSPI #0 device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on end # LPC/eSPI + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # eSPI Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller device pci 1f.3 off end # Intel HDA |