diff options
author | Peichao Wang <peichao.wang@bitland.corp-partner.google.com> | 2019-09-02 10:10:57 +0800 |
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committer | Martin Roth <martinroth@google.com> | 2019-09-09 23:45:33 +0000 |
commit | 0328a723b8d5d874e1528cda09a9e85d436a66f8 (patch) | |
tree | 2733efe5fd4335bf945c87b93b145dcfd1166162 /src/mainboard/google/hatch/variants/akemi/variant.c | |
parent | 80d0b01b38049775750c14cb0e0d978afb780ca1 (diff) |
mb/google/hatch: Distinguish SKU1 and 2 for eMMC and SSD respectively
1. SKU1 for eMMC
2. SKU2 for SSD
BUG=b:140008849, b:140573677
TEST=Verify SSD is disabled when SKU ID = 2/4/21/22
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I827e6f1420801d43e0eb4708b8b8ad1692ef7e9f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35204
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/hatch/variants/akemi/variant.c')
-rw-r--r-- | src/mainboard/google/hatch/variants/akemi/variant.c | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/akemi/variant.c b/src/mainboard/google/hatch/variants/akemi/variant.c new file mode 100644 index 0000000000..0717e810ce --- /dev/null +++ b/src/mainboard/google/hatch/variants/akemi/variant.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <soc/pci_devs.h> +#include <ec/google/chromeec/ec.h> + +void variant_devtree_update(void) +{ + uint32_t sku_id; + struct device *emmc_host; + struct device *ssd_host; + config_t *cfg = config_of_path(SA_DEVFN_ROOT); + emmc_host = pcidev_path_on_root(PCH_DEVFN_EMMC); + ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA); + + /* SKU ID 2 doesn't have a eMMC device, hence disable it. */ + sku_id = get_board_sku(); + if (sku_id == 2) { + if (emmc_host == NULL) + return; + emmc_host->enabled = 0; + cfg->ScsEmmcHs400Enabled = 0; + } + + /* SKU ID 1 doesn't have a SSD device, hence disable it. */ + if (sku_id == 1) { + if (ssd_host == NULL) + return; + ssd_host->enabled = 0; + cfg->SataSalpSupport = 0; + cfg->SataMode = 0; + cfg->SataPortsEnable[1] = 0; + cfg->SataPortsDevSlp[1] = 0; + cfg->satapwroptimize = 0; + } +} |