soc/intel/common: add PAD_CFG_NF_BUF_TRIG macro

In the case there is no the circuit diagram for motherboard, the
PCH/SoC GPIOs config is based on information from the inteltool
dump. However, available macros from gpio_defs.h can't define the
pad configuration from this dump:

0x0440: 0x0000002084000500 GPP_A8   CLKRUN#
0x0448: 0x0000102184000600 GPP_A9   CLKOUT_LPC0
0x0450: 0x0000102284000600 GPP_A10  CLKOUT_LPC1

To convert these raw DW0/DW1 register values to macros, the following
parameters must be set:

  func   - pad function,
  pull   - termination,
  rst    - pad reset config,
  trig   - rx level/edge configuration,
  bufdis - rx/tx (in/output) buffer disable.

The patch resolves the above problem by adding a new macro for the
native function configuration:

  PAD_CFG_NF_BUF_TRIG(pad, pull, rst, func, bufdis, trig)

These changes were tested on Asrock H110M-DVS motherboard [2].
It also resolves the problem of automatically creating pads
configuration [3,4]

[1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH
    Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2,
    February 2019, Document Number: 332691-003EN
    https://www.intel.com/content/dam/www/public/us/en/documents/
    datasheets/100-series-chipset-datasheet-vol-2.pdf
[2] https://review.coreboot.org/c/coreboot/+/33565
[3] https://github.com/maxpoliak/pch-pads-parser/issues/1
[4] https://github.com/maxpoliak/pch-pads-parser/commit/215d303

Change-Id: If9fe50ff9a680633db6228564345200c0e1ee3ea
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34337
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

0 files changed, 0 insertions, 0 deletions