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authorJamie Chen <jamie.chen@intel.com>2020-04-16 01:42:51 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-05-13 12:04:32 +0000
commit741099239194b01ef153a7b41a9d8389b0b06f8e (patch)
treea3856989ebd1b74fa2e66d5590c53f5192e1d82c /src/mainboard/google/hatch/Kconfig
parent92ba06fb3e6a5ba089305b6739b1b4344984ba37 (diff)
mb/google/puff: add a region to cache SPD data
This patch adds a SPI rom region RW_SPD_CACHE on Puff and it can be used on spd_cache to reduce reading SPD data from SODIMM by smbus. It's for saving the boot time and it can be used to trigger MRC retraining when memory DIMM is changed. BUG=b:146457985 BRANCH=None TEST=Build puff successfully and verified below two items. 1. To change memory DIMM can trigger retraining. 2. one DIMM save the boot time : 158ms two DIMM save the boot time : 265ms Change-Id: I8d07fddf113a767d62394cb31e33b56f22f74351 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Diffstat (limited to 'src/mainboard/google/hatch/Kconfig')
-rw-r--r--src/mainboard/google/hatch/Kconfig9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 6168e13140..8404eaa3f7 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -79,10 +79,19 @@ config DRIVER_TPM_SPI_BUS
config UART_FOR_CONSOLE
default 0
+if ROMSTAGE_SPD_CBFS
config FMDFILE
string
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB.fmd" if BOARD_ROMSIZE_KB_16384
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if BOARD_ROMSIZE_KB_32768
+endif
+
+if ROMSTAGE_SPD_SMBUS
+config FMDFILE
+ string
+ default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB-spd.fmd" if BOARD_ROMSIZE_KB_16384
+ default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-spd.fmd" if BOARD_ROMSIZE_KB_32768
+endif
config MAINBOARD_DIR
string