mb/google/guybrush/var/nipperkin: Override GPIO configuration

SOC_PEN_DETECT_ODL, SOC_SAR_INT_L and WWAN_AUX_RESET_L are not connected
in nipperkin. Override those GPIO configurations.

BUG=None
TEST=Build and boot to OS in Nipperkin.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7e497f83593472ecf4927e5379e1dd7786e77e62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>

2 files changed, 45 insertions, 0 deletions

diff --git a/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc b/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc
index 88e75bde52..f7c97bafbf 100644
--- a/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc
+++ b/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc
@@ -1,3 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
+bootblock-y += gpio.c
+romstage-y += gpio.c
+ramstage-y += gpio.c
+
 subdirs-y += ./memory
diff --git a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c
new file mode 100644
index 0000000000..acdcc4f7f3
--- /dev/null
+++ b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <baseboard/variants.h>
+
+static const struct soc_amd_gpio override_gpio_table[] = {
+	/* Unused TP1056 */
+	PAD_NC(GPIO_4),
+	/* Unused TP1063 */
+	PAD_NC(GPIO_17),
+	PAD_NC(GPIO_18),
+};
+
+static const struct soc_amd_gpio override_early_gpio_table[] = {
+	PAD_NC(GPIO_18),
+};
+
+static const struct soc_amd_gpio override_pcie_gpio_table[] = {
+	PAD_NC(GPIO_18),
+};
+
+const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
+{
+	*size = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size)
+{
+	*size = ARRAY_SIZE(override_early_gpio_table);
+	return override_early_gpio_table;
+}
+
+const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size)
+{
+	*size = ARRAY_SIZE(override_pcie_gpio_table);
+	return override_pcie_gpio_table;
+}