diff options
| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2021-10-26 16:55:35 -0600 |
|---|---|---|
| committer | Karthik Ramasubramanian <kramasub@google.com> | 2021-10-27 23:22:53 +0000 |
| commit | b4182989d7f74e10633f136a3b176ddd803b2d8c (patch) | |
| tree | 51e6a5523c1b910c85d15f00515c8ccae23e064e /src/mainboard/google/guybrush/variants/nipperkin | |
| parent | d3c565e7452f24432ae2940a2e19c70fa2de8e83 (diff) | |
mb/google/guybrush: Move GSC_SOC_INT_L from GPIO_3 to GPIO_85
GSC_SOC_INT_L gpio is used by Google Security Chip (GSC) to interrupt
SoC when the SoC is in S0 state. Hence use GPIO_85 which is in S0 domain
and save the GPIO_3 in S5 domain for other use-cases. This move applies
to all board except:
* Guybrush
* Nipperkin board version 1
Update the GPIO configuration, device tree configuration accordingly.
BUG=b:202992077
TEST=Build and boot to OS in Guybrush and Nipperkin. Ensure that the SoC
<-> TPM communication is working fine.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I019f10f2f457ab81bcff77ce8ca609b2b40cb2ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/mainboard/google/guybrush/variants/nipperkin')
3 files changed, 29 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc b/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc index d147aa9a49..d6cd2623a2 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc @@ -9,4 +9,6 @@ bootblock-y += variant.c romstage-y += variant.c ramstage-y += variant.c +ramstage-y += ramstage.c + subdirs-y += ./memory diff --git a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c index 2699f2a1cf..9a098dbb66 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c @@ -18,6 +18,10 @@ static const struct soc_amd_gpio bid1_override_gpio_table[] = { PAD_GPO(GPIO_5, HIGH), /* SD_AUX_RESET_L */ PAD_GPO(GPIO_69, HIGH), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + /* Unused */ + PAD_NC(GPIO_85), }; /* This table is used by nipperkin variant with board version >= 2. */ @@ -33,6 +37,8 @@ static const struct soc_amd_gpio bid2_override_gpio_table[] = { }; static const struct soc_amd_gpio override_early_gpio_table[] = { + /* BID == 1: GSC_SOC_INT_L, BID > 1: Unused */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), PAD_NC(GPIO_18), /* SD_AUX_RESET_L */ PAD_GPO(GPIO_69, LOW), diff --git a/src/mainboard/google/guybrush/variants/nipperkin/ramstage.c b/src/mainboard/google/guybrush/variants/nipperkin/ramstage.c new file mode 100644 index 0000000000..10428050f0 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/nipperkin/ramstage.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <boardid.h> +#include <device/device.h> +#include <drivers/i2c/tpm/chip.h> +#include <soc/gpio.h> + +void variant_devtree_update(void) +{ + uint32_t board_ver = board_id(); + const struct device *cr50_dev = DEV_PTR(cr50); + struct drivers_i2c_tpm_config *cfg; + struct acpi_gpio cr50_irq_gpio = ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3); + + if (board_ver > 1) + return; + + cfg = config_of(cr50_dev); + cfg->irq_gpio = cr50_irq_gpio; +} |